# US 12,014,972 B2 · Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices

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- Number: US 12,014,972 B2
- Document ID: US12014972B2
- Status: Granted
- Kind: B2
- Application number: 17/403,154
- Filed: 2021-08-16
- Published: 2021-12-02
- Granted: 2024-06-18
- Earliest claimed: 2014-09-22
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ju-Il Choi; Kwang-Jin Moon; Byung-Lyul Park; Jin-Ho An; Atsushi Fujisaki
- Web page: https://patentgrep.com/patent/US12014972B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/48: Insulating materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary via electrode through a portion of a substrate, the preliminary via electrode including a conductive layer and a barrier layer surrounding a sidewall of the conductive layer;
partially removing the substrate to expose a portion of the preliminary via electrode;
forming a protection layer structure on the substrate to cover the exposed portion of the preliminary via electrode;
partially etching the protection layer structure and the barrier layer to form a protection layer pattern structure and a barrier layer pattern, respectively, wherein a portion of the conductive layer is exposed;
wet etching the exposed portion of the conductive layer to form a conductive pattern, wherein the barrier layer pattern is wet etched so that a portion of the barrier layer pattern above the conductive pattern has a gradually decreasing width from a bottom toward a top thereof, and the conductive pattern and the barrier layer pattern form a via electrode; and
forming a pad structure on the via electrode.

### Claim 2

A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary via structure through a portion of a substrate;
partially removing the substrate to expose a portion of the preliminary via structure;
forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed;
partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure;
wet etching the preliminary via structure to form a via structure; and
forming a pad structure on the via structure to have a flat top surface,
wherein the preliminary via structure comprises:
a preliminary via electrode comprising a conductive layer, and a barrier layer surrounding a sidewall of the conductive layer; and
an insulation layer surrounding a sidewall of the preliminary via electrode, and
wherein the wet etching the preliminary via structure comprises partially removing the conductive layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein partially etching the protection layer structure to form the protection layer pattern structure comprises:
forming a photoresist layer on the protection layer structure;
patterning the photoresist layer to form a photoresist pattern partially exposing the protection layer structure; and
etching the protection layer structure using the photoresist pattern as an etching mask.

### Claim 4 (depends on 2)

The method of claim 2, wherein the partially etching the protection layer structure to form the protection layer pattern structure comprises forming the protection layer pattern structure to include an alignment key.

### Claim 5 (depends on 2)

The method of claim 2, wherein the partially etching the protection layer structure comprises:
forming a photosensitive organic layer on the protection layer structure;
patterning the photosensitive organic layer to form an organic layer pattern partially exposing the protection layer structure;
curing the organic layer pattern; and
etching the protection layer structure using the organic layer pattern as an etching mask.

### Claim 6 (depends on 2)

The method of claim 2, wherein the wet etching comprises partially removing the conductive layer, the barrier layer, and the insulation layer to form a conductive pattern, a barrier layer pattern, and an insulation layer pattern.

### Claim 7 (depends on 2)

The method of claim 2, wherein the forming the pad structure on the via structure comprises an electroplating process using a plating solution containing a leveler and/or a suppressor.

### Claim 8 (depends on 7)

The method of claim 7, prior to performing the electroplating process:
forming a seed layer on the via structure and on the protection layer pattern structure.

### Claim 9 (depends on 2)

The method of claim 2, wherein the partially etching the protection layer structure comprises partially removing the insulation layer of the preliminary via structure to form an insulation layer pattern and to partially expose the barrier layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the wet etching comprises partially removing the exposed barrier layer and the conductive layer thereunder to form a barrier layer pattern and a conductive pattern, respectively, each of the conductive pattern and the barrier layer pattern having a respective top surface that is lower than that of the insulation layer pattern.

### Claim 11 (depends on 2)

The method of claim 2, wherein the partially etching the protection layer structure to form the protection layer pattern structure and to partially expose the preliminary via structure comprises partially removing the insulation layer and the barrier layer to form an insulation layer pattern and a barrier layer pattern, respectively, and to partially expose the conductive layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the wet etching comprises partially removing the exposed conductive layer to form a conductive pattern having a top surface lower than respective top surfaces of the barrier layer pattern and the insulation layer pattern.

### Claim 13 (depends on 12)

The method of claim 12, wherein the top surface of the conductive pattern is lower than a top surface of the substrate.