# US 12,014,969 B2 · Package structure and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,969 B2 - Document ID: US12014969B2 - Status: Granted - Kind: B2 - Application number: 17/460,836 - Filed: 2021-08-30 - Published: 2023-03-02 - Granted: 2024-06-18 - Earliest claimed: 2021-08-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Po-Chen Lai; Ming-Chih Yew; Li-Ling Liao; Chin-Hua Wang; Po-Yao Lin; Shin-Puu Jeng - Web page: https://patentgrep.com/patent/US12014969B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10W 74/134: {the encapsulations being in grooves in the semiconductor body} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 72/851: {Dispositions of multiple connectors or interconnections} - H10W 74/01: Manufacture or treatment - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/10: characterised by their shape or disposition - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package structure is provided. The package structure includes a redistribution structure over a substrate, a semiconductor die over the redistribution structure and electrically coupled to the substrate, and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die. The underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate. ## Claims ### Claim 1 A package structure, comprising: a redistribution structure over a substrate; a semiconductor die over the redistribution structure and electrically coupled to the substrate; and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die, wherein the underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate, the substrate includes a first insulating layer and a first conductive trace embedded in the first insulating layer, a bottom surface of the extension portion is lower than a bottom surface of the first conductive trace, and in a plan view, a direction from a geometric center of the redistribution structure to the corner of the semiconductor die is defined as a first direction, and an angle of the first direction and a longitudinal direction of the extension portion is less than about 15 degrees. ### Claim 2 (depends on 1) The package structure as claimed in claim 1, wherein in a plan view, the extension portion includes a portion outside of an area of the redistribution structure. ### Claim 3 (depends on 1) The package structure as claimed in claim 1, wherein the extension portion is isolated from the first conductive trace by the first insulating layer. ### Claim 4 (depends on 1) The package structure as claimed in claim 1, wherein: in a plan view, the extension portion includes a first sidewall located within an area of the semiconductor die and a second sidewall opposite to the first sidewall and located outside of the area of the semiconductor die, and a minimum distance between the first sidewall of the extension portion and the corner of the semiconductor die is greater than or equal to a minimum distance between the second sidewall of the extension portion and the corner of the semiconductor die. ### Claim 5 (depends on 1) The package structure as claimed in claim 1, wherein a sidewall of the extension portion includes an arcuate surface. ### Claim 6 (depends on 1) The package structure as claimed in claim 1, further comprising: a plurality of bonding elements interposing between the substrate and the redistribution structure and surrounded by the underfill material, wherein none of the bonding elements is located directly over the extension portion. ### Claim 7 A package structure, comprising: a plurality of bonding elements over a substrate; a redistribution structure over the bonding elements; a semiconductor die over the redistribution structure; and an underfill material comprising: a first portion surrounding the plurality of bonding elements; and a second portion embedded in the substrate, wherein in a plan view, a corner of the semiconductor die is confined within an area of the second portion, wherein in a plan view, a first direction from a geometric center of the redistribution structure extending to the corner of the semiconductor die is substantially parallel to a symmetry axis of the second portion. ### Claim 8 (depends on 7) The package structure as claimed in claim 7, wherein in a plan view, the second portion is entirely confined within an area of the redistribution structure. ### Claim 9 (depends on 7) The package structure as claimed in claim 7, wherein in a plan view, the second portion has an elliptical profile. ### Claim 10 (depends on 7) The package structure as claimed in claim 7, wherein a bottom surface of the second portion is higher than a bottom surface of the substrate. ### Claim 11 (depends on 7) The package structure as claimed in claim 7, wherein in a plan view, a length of the second portion along the first direction is greater than a width of the second portion along a second direction that is perpendicular to the first direction. ### Claim 12 (depends on 7) The package structure as claimed in claim 7, wherein: in a plan view, the second portion includes a first sidewall located within an area of the semiconductor die and a second sidewall opposite to the first sidewall and located outside of the area of the semiconductor die, and as measured in the first direction, a first distance between the first sidewall and the corner of the semiconductor die is greater than or equal to a second distance between the second sidewall and the corner of the semiconductor die. ### Claim 13 (depends on 12) The package structure as claimed in claim 12, wherein as measured in the first direction, a third distance between a corner of the redistribution structure and the second sidewall is less than the second distance. ### Claim 14 (depends on 7) The package structure as claimed in claim 7, further comprising: a package over the redistribution structure, wherein the underfill material comprises: a third portion embedded in the substrate, wherein in a plan view, a corner of the package is confined within an area of the third portion. ### Claim 15 A method for forming a package structure, comprising: bonding a semiconductor die to a first surface of a redistribution structure; bonding a package to the first surface of the redistribution structure; bonding a second surface of the redistribution structure to a substrate, wherein the substrate includes a first trench overlapping a corner of the semiconductor die and a second trench overlapping a corner of the package; and encapsulating the semiconductor die and the redistribution structure with an underfill material, wherein the first trench and the second trench of the substrate are filled with underfill material. ### Claim 16 (depends on 15) The method for forming the package structure as claimed in claim 15, wherein the redistribution structure is bonded to the substrate through a plurality of bonding elements, and the underfill material surrounds the plurality of bonding elements. ### Claim 17 (depends on 15) The method for forming the package structure as claimed in claim 15, wherein in a plan view, a symmetry axis of the first trench passes through the corner of the semiconductor die. ### Claim 18 (depends on 1) The package structure as claimed in claim 1, wherein the substrate further includes a second insulating layer below the first insulating layer and a second conductive trace embedded in the second insulating layer, and the bottom surface of the extension portion is higher than an upper surface of the second conductive trace. ### Claim 19 (depends on 15) The method for forming the package structure as claimed in claim 15, wherein the substrate further includes an insulating layer and a conductive trace embedded in the insulating layer, and a bottom surface of the first trench is lower than a bottom surface of the conductive trace. ### Claim 20 (depends on 1) The package structure as claimed in claim 1, wherein: in a plan view, the semiconductor die has a first sidewall and a second sidewall connected to the first sidewall at the corner, and the extension portion has a third sidewall, a fourth sidewall connected to the third sidewall, a fifth sidewall connected to the fourth sidewall, and a sixth sidewall connected to the fifth sidewall and the third sidewall, the third sidewall of the extension portion crosses the first sidewall of the semiconductor die, and the fifth sidewall of the extension portion crosses the second sidewall of the semiconductor die.