# US 12,014,966 B2 · Semiconductor memory device having composite dielectric film structure and methods of forming the same

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- Number: US 12,014,966 B2
- Document ID: US12014966B2
- Status: Granted
- Kind: B2
- Application number: 18/115,810
- Filed: 2023-03-01
- Published: 2023-06-29
- Granted: 2024-06-18
- Earliest claimed: 2021-02-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Sheng-Chieh Chen; Wei-Ming Wang; Ming-Lun Lee; Chih-Ren Hsieh; Ming Chyi Liu
- Web page: https://patentgrep.com/patent/US12014966B2

## CPC

- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 41/43: comprising only one type of peripheral transistor
- H10B 41/49: comprising different types of peripheral transistor
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10W 74/01: Manufacture or treatment
- H10W 74/147: {the encapsulations being multilayered}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including a first region and a second region;
a plurality of memory devices located in the first region;
a plurality of transistors each including a metal gate located in the second region;
a first dielectric layer extending over the plurality of transistors in the second region and over at least a portion of the plurality of memory devices located in the first region; and
a second dielectric layer extending over the first dielectric layer in the first region, wherein the second dielectric layer has a different composition and/or physical characteristics than the first dielectric layer, and the second dielectric layer does not extend over the memory devices in the first region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer contacts an upper surface of each of the metal gates of the plurality of transistors.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein each of the first dielectric layer and the second dielectric layer have a thickness that is between 5 nm and 30 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer comprises a dielectric material including at least one of silicon oxide formed using a tetraethoxysilane (TEOS) precursor, and a resist protective oxide (RPO) material.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer comprises a dielectric material including at least one of a buffer oxide material, a silicon nitride material, and a high-temperature oxide (HTO) material.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer contacts an upper surface of at least one memory device in the first region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the at least one memory device comprises:
a floating gate;
a control gate located above the floating gate; and
a select gate located on a first side of the floating gate and the control gate, wherein the first dielectric layer contacts an upper surface of the control gate.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the at least one memory device further comprises:
an erase gate located on a second side of the floating gate and the control gate, wherein a metal silicide layer is located on an upper surface of the select gate and on an upper surface of the erase gate.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first dielectric layer is not located over the metal silicide layer located on the upper surface of the select gate and on the upper surface of the erase gate.

### Claim 10

A semiconductor device, comprising:
a substrate including a first region and a second region, wherein an upper surface of the substrate is recessed in the first region relative to an upper surface of the substrate in the second region;
a plurality of memory devices located in the first region;
a plurality of transistors each including a metal gate located in the second region; and
a composite dielectric film structure comprising at least two dielectric layers extending over the plurality of transistors in the second region, wherein a lower surface of the composite dielectric film structure is co-planar with an upper surface of each of the memory devices.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a peripheral edge of the composite dielectric film structure is located within 300 nm of a boundary between the first region and the second region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the boundary between a memory region and a peripheral region is defined by a peripheral edge of an isolation feature located in the substrate.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising a plurality of conductive vias extending through the composite dielectric film structure, wherein the composite dielectric film structure extends continuously between the conductive vias in the second region.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein each of the transistors in the second region includes a metal gate, and the composite dielectric film structure is located over the metal gates of the plurality of transistors in the second region.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the composite dielectric film structure comprises at least two dielectric layers having different compositions and/or physical characteristics.

### Claim 16

A method of fabricating a semiconductor device, comprising:
forming a plurality of memory devices in a first region of a substrate;
forming a plurality of transistors, each including a metal gate, in a second region of the substrate;
forming a first dielectric material layer over the plurality of transistors in the second region and over a portion of each of the memory devices in the first region;
forming a second dielectric material layer over the first dielectric layer in the second region, wherein the second dielectric layer does not extend over the plurality of memory devices in the first region;
depositing a metal material layer over the semiconductor device;
heating the metal material layer to form a metal silicide layer over portions of the memory devices that are exposed through the first dielectric layer; and
performing an etching process to remove remaining portions of the metal material layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the first dielectric layer comprises forming the first dielectric layer over each of the metal gates of the plurality of transistors in the second region and over a control gate of each of the plurality of memory devices located in the first region.

### Claim 18 (depends on 16)

The method of claim 16, wherein forming the second dielectric layer comprises forming the second dielectric layer over the first dielectric layer in the second region such that a peripheral edge of the second dielectric layer is located within 300 nm of a boundary between the first region and the second region.

### Claim 19 (depends on 16)

The method of claim 16, wherein the metal material layer is heated to form the metal silicide layer over an upper surface of at least one of a select gate and a control gate of a memory device in the first region, and a portion of the first dielectric layer is located over a control gate of the memory device during the formation of the metal silicide layer and during the etching process to remove the remaining portions of the metal material layer.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
forming a conductive via through the first dielectric layer and the second dielectric layer and electrically contacting a source or drain region of a transistor in the second region.