# US 12,014,964 B2 · Semiconductor package having an electrically insulating core with exposed glass fibres

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- Number: US 12,014,964 B2
- Document ID: US12014964B2
- Status: Granted
- Kind: B2
- Application number: 17/986,306
- Filed: 2022-11-14
- Published: 2023-03-09
- Granted: 2024-06-18
- Earliest claimed: 2020-01-28
- Assignees: Infineon Technologies AG; Infineon Technologies Americas Corp.
- Applicants: Infineon Technologies AG
- Inventors: Eung San Cho; Tomasz Naeve; Petteri Palm
- Web page: https://patentgrep.com/patent/US12014964B2

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6875: {being on a metallic substrate, e.g. insulated metal substrates [IMS]}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 40/73: for cooling by change of state
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/635: {Through-vias}
- H10W 70/68: Shapes or dispositions thereof
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/738: {between a chip and a stacked discrete passive device}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes: an electrically insulating core and an electrically conductive first via extending through a periphery region of the core, the core having glass fibres interwoven with epoxy material and one or more regions where the glass fibres are exposed from the epoxy material; a power semiconductor die embedded in an opening in the core and having a first load terminal bond pad which faces a same direction as a first side of the core, a second load terminal bond pad which faces a same direction as a second side of the core, and a control terminal bond pad; a resin that encases the power semiconductor die; a first contact pad plated on the first via at the second side of the core; and a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.

## Claims

### Claim 1

A semiconductor package, comprising:
an electrically insulating core having a first side, a second side opposite the first side and configured for mounting to a substrate, and an electrically conductive first via extending through a periphery region of the core, the periphery region defining an opening in the core, the core comprising glass fibres interwoven with epoxy material, the core having one or more regions at the second side where the glass fibres are exposed from the epoxy material;
a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core and comprising a first load terminal bond pad at a first side which faces a same direction as the first side of the core, a second load terminal bond pad at a second side which faces a same direction as the second side of the core, and a control terminal bond pad at the first side or the second side of the power semiconductor die;
a resin in the opening in the core and that encases the power semiconductor die;
a first contact pad plated on the first via at the second side of the core; and
a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, further comprising:
a third contact pad plated on the second load terminal bond pad of the power semiconductor die at the second side of the core.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, further comprising:
a fourth contact pad plated on the control terminal bond pad of the power semiconductor die at the first or second side of the core.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, further comprising:
a solder mask partly covering the one or more regions at the second side of the core where the glass fibres are exposed from the epoxy material.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the resin is coplanar with the first side of the core and no glass fibres are exposed from the epoxy material at the first side of the core.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, further comprising:
a recess at the second side of the core.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein the recess is deeper than the first contact pad at the second side of the core.

### Claim 8 (depends on 6)

The semiconductor package of claim 6, further comprising:
a solder ball in the recess.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the second side of the core is dry plasma etched, and wherein the first side of the core is not dry plasma etched.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein the first load terminal bond pad of the power semiconductor die is a drain bond pad, and wherein the second load terminal bond pad of the power semiconductor die is a source bond pad.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, wherein the exposed glass fibres are hidden from plain view when the second side of the core is in a mounted position on a substrate.