# US 12,014,961 B2 · Method of semiconductor overlay measuring and method of semiconductor structure manufacturing

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- Number: US 12,014,961 B2
- Document ID: US12014961B2
- Status: Granted
- Kind: B2
- Application number: 17/233,560
- Filed: 2021-04-19
- Published: 2022-10-20
- Granted: 2024-06-18
- Earliest claimed: 2021-04-19
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Kai-Ping Chan; Tsu-Wen Huang; Kai Lee
- Web page: https://patentgrep.com/patent/US12014961B2

## CPC

- G06T 7/74: {involving reference images or patches}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- G03F 7/70633: {Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching}
- G06T 7/001: {using an image reference approach}
- H10B 12/033: {the capacitor extending over the transistor}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/716: {having vertical extensions}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G06T 2207/30148: Semiconductor; IC; Wafer
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 46/301: {for alignment}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of semiconductor overlay measuring includes following operations. Provide a test substrate. Conductive structures are located in the test substrate and exposed from a top surface of the test substrate. Positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate. Mark first marks corresponding to the exposed conductive structures on the first image. Form a test capping layer with capacitor openings on the top surface of the test substrate. Move the test substrate to the standard position and capturing a second image of a top surface of the test capping layer. Identify the capacitor openings on the second image with second marks. Compare the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.

## Claims

### Claim 1

A method of semiconductor overlay measuring, comprising:
providing a test substrate, wherein a plurality of conductive structures are disposed in the test substrate and exposed from a top surface of the test substrate;
positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate;
marking a plurality of first marks on the first image, wherein the first marks are direct to the exposed conductive structures within the test substrate in the first image;
after the first image is captured, forming a test capping layer on the top surface of the test substrate, wherein the test capping layer has a plurality of capacitor openings;
moving the test substrate to the standard position and capturing a second image of a top surface of the test capping layer;
identifying the capacitor openings on the second image with a plurality of second marks; and
comparing the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first marks correspond to profiles of the exposed conductive structures on the test substrate, and the second marks correspond to profiles of the capacitor openings.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first and second images are captured by an electronic microscope.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second marks are identified through a pattern recognition process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the exposed conductive structures are arranged in rows extending along a first direction, the rows are arranged in a second direction perpendicular to the first direction, the marking the first marks on the first image further comprise:
marking reference frames arranged on a straight line along one of the first and second directions; and
marking the first marks according to the reference frames.

### Claim 6 (depends on 5)

The method of claim 5, wherein the comparing the first marks with the second marks comprises:
marking the reference frames on the second image; and
marking the first marks on the second image according the reference frames.

### Claim 7 (depends on 1)

The method of claim 1, wherein the conductive structures are surrounded by streets, and a plurality of measuring marks are located in the streets.

### Claim 8 (depends on 7)

The method of claim 7, wherein the standard position of the test substrate is defined by the measuring marks.

### Claim 9 (depends on 1)

A method of semiconductor structure manufacturing, comprising:
processing the method of claim 1 to have the position offset; and
providing a substrate with exposed conductive structures in the standard position and forming a capping layer over the substrate, wherein the capping layer is provided by an apparatus used to form the test capping layer, the position offset is received by the apparatus, so that capacitor openings of the capping layer are respectively aligned with the conductive structures exposed from a top surface of the substrate, and the capacitor openings extend along a direction perpendicular to the top surface of the substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein each of the conductive structures of the substrate comprising an active area within the substrate and a metal contact connected to the active area and exposed from the top surface of the substrate.

### Claim 11 (depends on 9)

The method of claim 9, wherein the capping layer comprises dielectric material.

### Claim 12 (depends on 9)

The method of claim 9, wherein the conductive structures on the substrate are surrounded by streets, and a plurality of measuring marks are located in the streets.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
forming capacitors in the capacitor openings of the substrate, wherein the capacitors extend along the direction in which the capacitor openings extend.

### Claim 14 (depends on 13)

The method of claim 13, wherein each of the capacitors comprises:
a dielectric container formed within a corresponding one of the capacitor opening and covering a corresponding one of the exposed conductive structures of the substrate; and
a conductive material filled with the dielectric container.

### Claim 15 (depends on 14)

The method of claim 14, wherein the conductive structures comprise transistors, the capacitors are connected to the transistor respectively to form memory units.