# US 12,014,960 B2 · Etch profile control of polysilicon structures of semiconductor devices

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- Number: US 12,014,960 B2
- Document ID: US12014960B2
- Status: Granted
- Kind: B2
- Application number: 17/234,138
- Filed: 2021-04-19
- Published: 2021-08-19
- Granted: 2024-06-18
- Earliest claimed: 2017-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuo-Cheng Chiang; Chih-Hao Wang; Kuan-Ting Pan
- Web page: https://patentgrep.com/patent/US12014960B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively.

## Claims

### Claim 1

A method, comprising:
doping a fin structure;
depositing an oxide layer on a top surface and sidewalls of the fin structure;
oxidizing the fin structure through the top surface at a first oxidation rate to form a first oxide region; and
oxidizing the fin structure through the sidewalls at a second oxidation rate to form a second oxide region, wherein the second oxidation rate is less than the first oxidation rate.

### Claim 2 (depends on 1)

The method of claim 1, wherein doping the fin structure comprises:
forming an amorphous region on the fin structure, the amorphous region comprising an amorphous material; and
doping the amorphous region.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the amorphous region comprises:
depositing a layer of insulating material on the fin structure;
forming a recessed region within the layer of insulating material and on the fin structure;
depositing a layer of the amorphous material on the layer of insulating material to fill the recessed region; and
removing portions of the layer of amorphous material on the layer of insulating material to substantially coplanarize a top surface of the layer of insulating material with top surfaces of other portions of the layer of amorphous material within the recessed region.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a polysilicon structure on the first and second oxide regions; and
replacing the polysilicon structure with a metal gate electrode.

### Claim 5 (depends on 1)

The method of claim 1, wherein doping the fin structure comprises doping an amorphous silicon region of the fin structure using a fluorine or an oxygen dopant.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a source/drain region on a portion of the fin structure.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a polysilicon structure on the first and second oxide regions;
removing the polysilicon structure;
etching portions of the first and second oxide regions exposed by removing the polysilicon structure; and
depositing a metal gate electrode on the first and second oxide regions.

### Claim 8 (depends on 7)

The method of claim 7, wherein forming the polysilicon structure comprises:
depositing a polysilicon layer on the first and second oxide regions; and
etching first and second portions of the polysilicon layer at first and second etch rates, the first etch rate being greater than the second etch rate.

### Claim 9

A semiconductor device, comprising:
a fin structure; and
an oxide layer on the fin structure, comprising:
a first portion of the oxide layer on a top surface of the fin structure and comprising a first thickness; and
a second portion of the oxide layer on a sidewall of the fin structure and comprising a second thickness less than the first thickness, wherein the second thickness is substantially constant along the sidewall of the fin structure.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a layer of amorphous silicon on the top surface of the fin structure.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, further comprising a gate electrode on the oxide layer.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further comprising a dielectric layer on the first and second portions of the oxide layer.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, further comprising spacers on sidewalls of a gate electrode, wherein the oxide layer extends under the spacers.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein a width of the first portion of the oxide layer is greater than a sum of (i) a width of the fin structure and (ii) two times the second thickness.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, further comprising:
an other fin structure; and
an other oxide layer on the other fin structure, comprising:
a first portion of the other oxide layer on a top surface of the other fin structure; and
a second portion of the other oxide layer on a sidewall of the other fin structure, wherein a first thickness of the first portion of the other oxide layer is substantially equal to a second thickness of the second portion of the other oxide layer.

### Claim 16

A semiconductor device, comprising:
a fin structure comprising a first width; and
an oxide layer on the fin structure, comprising:
a first portion of the oxide layer on a top surface of the fin structure and comprising a first thickness and a second width; and
a second portion of the oxide layer on sidewalls of the fin structure and comprising a second thickness, wherein the second thickness is substantially constant along the sidewalls of the fin structure, and wherein the first portion of the oxide layer extends laterally beyond outer sidewalls of the second portion.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the first thickness is greater than the second thickness.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first thickness is greater than the second thickness by a value ranging from about 0.5 nm to about 3 nm.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, further comprising:
a dielectric layer on the oxide layer; and
a gate electrode on the dielectric layer.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, further comprising spacers on sidewalls of the gate electrode, wherein the oxide layer extends under the spacers.