# US 12,014,958 B2 · Microfeature workpieces and methods for forming interconnects in microfeature workpieces

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,014,958 B2
- Document ID: US12014958B2
- Status: Granted
- Kind: B2
- Application number: 18/047,049
- Filed: 2022-10-17
- Published: 2023-04-06
- Granted: 2024-06-18
- Earliest claimed: 2005-09-01
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: William M. Hiatt; Ross S. Dando
- Web page: https://patentgrep.com/patent/US12014958B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/0261: {characterised by the filling method or the material of the conductive fill}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

## Claims

### Claim 1

An integrated circuit structure, comprising:
an integrated circuit substrate having a conductive pad on a first face thereof and a through hole that extends through the integrated circuit substrate and the pad; and
an electrically conductive interconnect in the through hole and through and onto the pad, the electrically conductive interconnect filling the through hole adjacent the first face, and including a recess therein adjacent a second face of the integrated circuit substrate, the recess defining inner walls of the conductive electrode, wherein the recess has a depth less than or equal to a thickness of an insulating layer over the second face of the integrated circuit substrate.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a conductive bump that extends into the recess and directly contacts the inner walls of the conductive electrode.

### Claim 3 (depends on 2)

The integrated circuit structure of claim 2, wherein the conductive bump comprises nickel (Ni).

### Claim 4 (depends on 2)

The integrated circuit structure of claim 2, wherein the conductive bump completely fills the recess.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, further comprising a seed layer between the electrically conductive interconnect and the substrate in the through hole.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein the seed layer comprises copper (Cu).

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein the electrically conductive interconnect comprises copper (Cu), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), tin (Sn), or a combination thereof.