# US 12,014,957 B2 · Semiconductor device having a source/drain contact plug with an upwardly protruding portion

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- Number: US 12,014,957 B2
- Document ID: US12014957B2
- Status: Granted
- Kind: B2
- Application number: 17/701,275
- Filed: 2022-03-22
- Published: 2022-07-07
- Granted: 2024-06-18
- Earliest claimed: 2019-09-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sungmoon Lee; Minchan Gwak; Heonjong Shin; Yongsik Jeong; Yeongchang Roh; Doohyun Lee; Sunghun Jung; Sangwon Jee
- Web page: https://patentgrep.com/patent/US12014957B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/067: {by modifying the pattern of conductive parts}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

## Claims

### Claim 1

A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a gate electrode extending in a second direction to intersect the active region;
channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate electrode;
source/drain regions on both sides of the gate electrode and connected to the channel layers;
an interlayer insulating layer covering the source/drain regions;
a contact plug penetrating through the interlayer insulating layer and connected to each of the source/drain regions,
wherein the contact plug includes a first portion extending in the second direction, and a second portion protruding upwardly from an end of the first portion and defining a recess region of the contact plug, and
wherein a first length of the second portion in the second direction is less than a second length of the recess region in the second direction; and
a contact insulating layer filling the recess region of the contact plug.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein opposite side surfaces, in the second direction, of the second portion have negative slopes at first and second obtuse angles with respect to an upper surface of the first portion, respectively.

### Claim 3 (depends on 2)

The semiconductor device of claim 2,
wherein the first and second obtuse angles are substantially a same.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein a third length, in the first direction, of an upper surface of the second portion in the first direction is greater than a fourth length, in the first direction, of a lower surface of the first portion.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate capping layer on the gate electrode and having a recessed edge in a shape recessed from an upper surface of the gate capping layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5,
wherein the recessed edge of the gate capping layer is adjacent to the recess region of the contact plug in the first direction.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein an edge of the gate capping layer, which is not recessed, contacts the second portion of the contact plug.

### Claim 8 (depends on 5)

The semiconductor device of claim 5,
wherein the contact insulating layer further fills the recessed edge of the gate capping layer.

### Claim 9 (depends on 5)

The semiconductor device of claim 5,
wherein the gate capping layer has a lower curved surface that is convex downwardly.

### Claim 10

A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a gate electrode extending in a second direction to intersect the active region;
channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate electrode;
source/drain regions on both sides of the gate electrode and connected to the channel layers;
a contact plug connected to each of the source/drain regions on each of the source/drain regions; and
a gate capping layer on the gate electrode and having a width greater than a width of the gate electrode,
wherein the contact plug includes a first portion extending in the second direction, and a second portion protruding upwardly from a portion of the first portion and defining at least one recess region of the contact plug, and
wherein a length of an upper surface of the second portion in the first direction is greater than a length of a lower surface of the first portion in the first direction.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a length of the second portion in the second direction is less than a second length of the at least one recess region in the second direction.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the second portion is spaced apart from both ends of the first portion in the second direction.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the at least one recess region includes first and second recessed regions on both sides of the second portion in the second direction.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein a first side surface of the second portion in the second direction has a positive slope, and a second side surface of the second portion opposing the first side surface has a negative slope.

### Claim 15

A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a gate electrode extending in a second direction to intersect the active region;
source/drain regions on both sides of the gate electrode;
a contact plug connected to each of the source/drain regions;
a gate capping layer on the gate electrode and having a recessed edge in a shape recessed from an upper surface; and
a contact insulating layer filling the recessed edge of the gate capping layer,
wherein the contact plug includes a first portion extending in the second direction, and a second portion protruding upwardly from a portion of the first portion and defining at least one recess region of the contact plug, and
wherein the contact insulating layer fills the at least one recess region of the contact plug.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a first length of the second portion in the second direction is less than a second length of the recess region in the second direction.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a third length of an upper surface of the second portion in the first direction is greater than a fourth length of a lower surface of the first portion in the first direction.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the recessed edge of the gate capping layer is in adjacent to the recess region of the contact plug in the first direction.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein an edge of the gate capping layer, which is not recessed, is contact with the second portion of the contact plug.