# US 12,014,951 B2 · Semi-damascene structure with dielectric hardmask layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,951 B2 - Document ID: US12014951B2 - Status: Granted - Kind: B2 - Application number: 17/390,035 - Filed: 2021-07-30 - Published: 2022-11-24 - Granted: 2024-06-18 - Earliest claimed: 2021-05-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hoonseok Seo; Euibok Lee; Taeyong Bae - Web page: https://patentgrep.com/patent/US12014951B2 ## CPC - H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10P 50/71: {using masks for conductive or resistive materials} - H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating} - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 20/0633: {using subtractive patterning of the conductive members} - H10W 20/075: {of multilayered thin functional dielectric layers} - H10W 20/42: Vias, e.g. via plugs - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 20/098: {by filling between adjacent conductive parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer. ## Claims ### Claim 1 A method of manufacturing a semi-damascene structure of a semiconductor device, the method comprising: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the at least one 1st photoresist pattern; removing the at least one 1st photoresist pattern; forming a metal structure in the at least one via hole such that the metal structure fills in the at least one via hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the at least one 1st trench with a 2nd intermetal dielectric layer. ### Claim 2 (depends on 1) The method of claim 1, wherein the patterning the metal structure comprises: forming a 2nd hardmask layer on the metal structure, and patterning the 2nd hardmask layer; and wherein the patterning the metal structure comprises performing direct etching on the metal structure according to the patterned 2nd hardmask layer, after which the 2nd hardmask layer is removed. ### Claim 3 (depends on 2) The method of claim 2, wherein the 2nd hardmask layer has material composition with an etch rate or etch selectivity which is different from that of material composition of the 1st hardmask layer. ### Claim 4 (depends on 3) The method of claim 3, wherein after the metal structure is patterned and the 2nd hardmask layer is removed, at least a portion of the 1st hardmask layer is exposed upward through the at least one 1st trench and remains on the 1st intermetal dielectric layer. ### Claim 5 (depends on 4) The method of claim 4, further comprising: forming at least one 2nd photoresist pattern having at least one 2nd trench on the 2nd hardmask layer, wherein the patterning the metal structure comprising performing direct etching on the metal structure according to the patterned 2nd hardmask layer after which the 2nd hardmask layer is removed is performed according to the 2nd photoresist pattern, after which the 2nd photoresist pattern is removed. ### Claim 6 (depends on 3) The method of claim 3, wherein after the metal structure is patterned and the 2nd hardmask layer is removed, the 1st hardmask layer is exposed upward through the at least one 1st trench and remains on the 1st intermetal dielectric layer with an upper portion of the 1st hardmask layer exposed upward through the at least one 1st trench being vertically dented. ### Claim 7 (depends on 3) The method of claim 3, wherein the 2nd hardmask layer has material composition with an etch rate or etch selectivity which is the same as or substantially the same as that of material composition of the 1st hardmask layer. ### Claim 8 (depends on 7) The method of claim 7, wherein after the patterning the metal structure, the 2nd hardmask layer and the 1st hardmask layer, which is exposed upward through the at least one 1st trench, are removed. ### Claim 9 (depends on 8) The method of claim 8, further comprising: forming at least one 2nd photoresist pattern having at least one 2nd trench on the 2nd hardmask layer, wherein the patterning the 2nd hardmask layer and the metal structure by direct etching is performed according to the 2nd photoresist pattern, after which the 2nd photoresist pattern is removed. ### Claim 10 (depends on 7) The method of claim 7, wherein after the patterning the metal structure, the 2nd hardmask layer and the 1st hardmask layer, which is exposed upward through the at least one 1st trench, are removed, and a portion of the 1st hardmask layer formed below the metal structure above the 1st intermetal dielectric layer and exposed toward the at least one 1st trench are laterally dented. ### Claim 11 (depends on 3) A method of manufacturing a semiconductor device, the method comprising: forming a substrate in which at least one transistor structure is included; and performing the method of claim 3 to obtain a semi-damascene structure such that the metal structure is connected to an active region of the at least one transistor structure.