# US 12,014,934 B2 · Semiconductor substrate structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,934 B2 - Document ID: US12014934B2 - Status: Granted - Kind: B2 - Application number: 17/980,556 - Filed: 2022-11-04 - Published: 2023-05-04 - Granted: 2024-06-18 - Earliest claimed: 2021-11-04 - Applicants: Dyi-Chung Hu - Inventors: Dyi-Chung Hu - Web page: https://patentgrep.com/patent/US12014934B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 70/635: {Through-vias} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor substrate structure includes a first group of circuit structure and a second group of circuit structure. The first group of circuit structure includes multiple first circuit layers and a first bonding layer. The second group of circuit structure includes multiple second circuit layers and a second bonding layer. The second group of circuit structure is disposed on the first group of circuit structure and is electrically connected to the first group of circuit structure. The first bonding layer is bonded to the second bonding layer to form a multilayer redistribution structure. A manufacturing method of the semiconductor substrate structure is also provided. ## Claims ### Claim 1 A semiconductor substrate structure, comprising: a first circuit structure, comprising a plurality of first circuit layers and a first bonding layer; and a second circuit structure, comprising a plurality of second circuit layers and a second bonding layer, wherein the second circuit structure is disposed on the first circuit structure and is electrically connected to the first circuit structure, and the first bonding layer is bonded to the second bonding layer to form a multilayer redistribution structure. ### Claim 2 (depends on 1) The semiconductor substrate structure according to claim 1, wherein the first bonding layer comprises a plurality of first bonding members and a first bonding dielectric layer, and the second bonding layer comprises a plurality of second bonding members and a second bonding dielectric layer, the first bonding members are in direct contact with the second bonding members, and the first bonding dielectric layer is in direct contact with the second bonding dielectric layer. ### Claim 3 (depends on 1) The semiconductor substrate structure according to claim 1, wherein a dielectric layer in the first circuit structure and a dielectric layer in the second circuit structure are organic thin films. ### Claim 4 (depends on 1) The semiconductor substrate structure according to claim 1, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are the same. ### Claim 5 (depends on 1) The semiconductor substrate structure according to claim 1, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are different. ### Claim 6 (depends on 1) The semiconductor substrate structure according to claim 1, wherein each of the first circuit layers comprises two adjacent first circuits, and a first pitch is provided between center points of the two adjacent first circuits, each of the second circuit layers comprises two adjacent second circuits, and a second pitch is provided between center points of the two adjacent second circuits, the first pitch of each of the first circuit layers is smaller than the second pitch of each of the second circuit layers, and the first circuit structure comprises a first surface and an opposing second surface, the second circuit structure comprises a third surface and an opposing fourth surface, and the first surface is bonded to the third surface. ### Claim 7 (depends on 3) The semiconductor substrate structure according to claim 3, wherein a first pitch and a second pitch are minimum pitches of each layer. ### Claim 8 (depends on 1) The semiconductor substrate structure according to claim 1, wherein a number of the first circuit layers of the first circuit structure is the same as a number of the second circuit layers of the second circuit structure. ### Claim 9 (depends on 1) The semiconductor substrate structure according to claim 1, wherein a number of the first circuit layers of the first circuit structure is different from a number of the second circuit layers of the second circuit structure. ### Claim 10 (depends on 9) The semiconductor substrate structure according to claim 9, wherein the number of the first circuit layers of the first circuit structure and the number of the second circuit layers of the second circuit structure are one layer or two layers. ### Claim 11 A semiconductor substrate structure, comprising: a first circuit structure, comprising a plurality of first circuit layers and a first bonding layer; a second circuit structure, comprising a plurality of second circuit layers and a second bonding layer, wherein the second circuit structure is disposed on the first circuit structure and is electrically connected to the first circuit structure, and the first bonding layer is bonded to the second bonding layer; and a third circuit structure, comprising a plurality of third circuit layers and a third bonding layer, wherein the second circuit structure is disposed between the first circuit structure and the third circuit structure and are electrically connected with each other, and the second circuit structure comprises another bonding layer relative to the first circuit structure, and the another bonding layer is bonded to the third bonding layer to form a multilayer redistribution structure. ### Claim 12 (depends on 11) The semiconductor substrate structure according to claim 11, wherein a dielectric layer in the first circuit structure and a dielectric layer in the second circuit structure are organic thin films. ### Claim 13 (depends on 11) The semiconductor substrate structure according to claim 11, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are the same. ### Claim 14 (depends on 11) The semiconductor substrate structure according to claim 11, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are different. ### Claim 15 (depends on 11) The semiconductor substrate structure according to claim 11, wherein a number of the first circuit layers of the first circuit structure is the same as a number of the second circuit layers of the second circuit structure. ### Claim 16 (depends on 11) The semiconductor substrate structure according to claim 11, wherein a number of the first circuit layers of the first circuit structure is different from a number of the second circuit layers of the second circuit structure. ### Claim 17 (depends on 16) The semiconductor substrate structure according to claim 16, wherein the number of the first circuit layers of the first circuit structure and the number of the second circuit layers of the second circuit structure are one layer or two layers. ### Claim 18 (depends on 11) The semiconductor substrate structure according to claim 11, wherein a coefficient of thermal expansion of the third bonding layer is smaller than a coefficient of thermal expansion of the first bonding layer and a coefficient of thermal expansion of the second bonding layer. ### Claim 19 (depends on 11) The semiconductor substrate structure according to claim 11, wherein a thickness of the third circuit structure is greater than a thickness of the first circuit structure and a thickness of the second circuit structure, the third circuit structure comprises a plurality of third circuit layers and a third bonding layer, each of the first circuit layers comprises two adjacent first circuits, and a first pitch is provided between center points of the two adjacent first circuits, each of the second circuit layers comprises two adjacent second circuits, and a second pitch is provided between center points of the two adjacent second circuits, each of the third circuit layers comprises two adjacent third circuits, and a third pitch is provided between center points of the two adjacent third circuits, the third pitch is greater than the first pitch and the second pitch, the first circuit structure comprises a first surface and an opposing second surface, the second circuit structure comprises a third surface and an opposing fourth surface, the third circuit structure comprises a fifth surface and an opposing sixth surface, the first surface is bonded to the third surface, the fourth surface is bonded to the fifth surface, a direction from the second surface to the sixth surface passes through the first surface, the third surface, the fourth surface, and the fifth surface. ### Claim 20 A manufacturing method of a semiconductor substrate structure, comprising: forming a first circuit structure on a first temporary carrier, wherein the first circuit structure comprises a plurality of first circuit layers and a first bonding layer; forming a second circuit structure on a second temporary carrier, wherein the second circuit structure comprises a plurality of second circuit layers and a second bonding layer; and directly bonding the first circuit structure and the second circuit structure, so that the first bonding layer is bonded to the second bonding layer. ### Claim 21 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein the direct bonding is performed by Cu to Cu hybrid bonding or Cu to Cu direct bonding. ### Claim 22 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein forming the first bonding layer further comprises: forming a first micro bump on the first circuit layers; forming a first connecting bump on the first micro bump; forming a first bonding dielectric material layer to cover the first micro bump and the first connecting bump; and forming a first bonding member and a first bonding dielectric layer by performing a planarization process. ### Claim 23 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein a planarization process is performed with a grinding wheel until a top surface of a first connecting bump is exposed, so that top surfaces of a first bonding member and a first bonding dielectric layer are coplanar. ### Claim 24 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein the forming the second bonding layer further comprises: forming a second micro bump on the second circuit layers; forming a second connecting bump on the second micro bump; and forming a second bonding dielectric material layer to cover the second micro bump and the second connecting bump. ### Claim 25 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein a planarization process is performed with a grinding wheel until a top surface of a second connecting bump is exposed, so that top surfaces of a second bonding member and a second bonding dielectric layer of are coplanar. ### Claim 26 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein forming the first bonding layer further comprises: forming a first photosensitive dielectric layer on the first circuit layers; patterning the first photosensitive dielectric layer and curing the first photosensitive dielectric layer to form a plurality of openings exposing the first circuit layer below; forming a first seed crystal layer to cover the first patterned photosensitive dielectric layer, wherein the openings are filled by a part of the first seed crystal layer; and performing a planarization process with a grinding wheel, such that each top-surface of a first bonding member and a top surface of a first bonding dielectric layer are coplanar. ### Claim 27 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein forming the second bonding layer further comprises: forming a second photosensitive dielectric layer on the second circuit layers; patterning the second photosensitive dielectric layer and curing the second photosensitive dielectric layer to form a plurality of openings exposing the second circuit layer below; forming a second seed crystal layer to cover the second patterned photosensitive dielectric layer, wherein the openings are filled by a part of the second seed crystal layer; and forming a second metal layer by performing an electroplating process, and performing a planarization process with a grinding wheel, such that each top-surface of a second bonding member and a top surface of a second bonding dielectric layer are coplanar. ### Claim 28 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein after the first circuit structure and the second circuit structure are assembled, the first temporary carrier is removed by a first releasing layer. ### Claim 29 (depends on 28) The manufacturing method of the semiconductor substrate structure according to claim 28, wherein after removing the first temporary carrier, a plurality of conductive connecting members are formed on the first circuit structure, wherein each of the conductive connecting members comprises a conductive pillar and a conductive cap, and the conductive cap is formed on the conductive pillar. ### Claim 30 (depends on 29) The manufacturing method of the semiconductor substrate structure according to claim 29, wherein the semiconductor substrate structure is configured to dispose a semiconductor chip and an external terminal on two opposite sides, and comprises: bonding the semiconductor chip on the semiconductor substrate structure; forming an underfill on the semiconductor substrate structure; encapsulating the semiconductor substrate structure and the semiconductor chip; removing the second temporary carrier by a second releasing layer; and forming the external terminal on the second circuit structure. ### Claim 31 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein a dielectric layer in the first circuit structure and a dielectric layer in the second circuit structure are organic thin films. ### Claim 32 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are the same. ### Claim 33 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are different. ### Claim 34 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein a number of the first circuit layers of the first circuit structure is the same as a number of the second circuit layers of the second circuit structure. ### Claim 35 (depends on 20) The manufacturing method of the semiconductor substrate structure according to claim 20, wherein a number of the first circuit layers of the first circuit structure is different from a number of the second circuit layers of the second circuit structure. ### Claim 36 (depends on 35) The manufacturing method of the semiconductor substrate structure according to claim 35, wherein the number of the first circuit layers of the first circuit structure and the number of the second circuit layers of the second circuit structure are one layer or two layers. ### Claim 37 (depends on 20) The semiconductor substrate structure according to claim 20, wherein each of the first circuit layers comprises two adjacent first circuits, and a first pitch is provided between center points of the two adjacent first circuits, each of the second circuit layers comprises two adjacent second circuits, and a second pitch is provided between center points of the two adjacent second circuits, the first pitch of each of the first circuit layers is smaller than the second pitch of each of the second circuit layers, and the first circuit structure comprises a first surface and an opposing second surface, the second circuit structure comprises a third surface and an opposing fourth surface, the first surface is bonded to the third surface, and a pitch of each layer is directed from the second surface to the fourth surface and passes through the first surface and the third surface. ### Claim 38 A manufacturing method of a semiconductor substrate structure, comprising: forming a first circuit structure on a first temporary carrier, wherein the first circuit structure comprises a plurality of first circuit layers and a first bonding layer; forming a second circuit structure on a second temporary carrier, wherein the second circuit structure comprises a plurality of second circuit layers and a second bonding layer; directly bonding the first circuit structure and the second circuit structure, so that the first bonding layer is bonded to the second bonding layer; forming a third circuit structure on the second circuit structure, wherein the third circuit structure comprises a plurality of third circuit layers and a third bonding layer; and bonding the second circuit structure and the third circuit structure, wherein the second circuit structure comprises another bonding layer relative to the first circuit structure, and the another bonding layer is bonded to the third bonding layer. ### Claim 39 (depends on 38) The manufacturing method of the semiconductor substrate structure according to claim 38, wherein a thickness of the third circuit structure is greater than a thickness of the first circuit structure and a thickness of the second circuit structure, each of the first circuit layers comprises two adjacent first circuits, and a first pitch is provided between center points of the two adjacent first circuits, each of the second circuit layers comprises two adjacent second circuits, and a second pitch is provided between center points of the two adjacent second circuits, each of the third circuit layers comprises two adjacent third circuits, and a third pitch is provided between center points of the two adjacent third circuits, the third pitch is greater than the first pitch and the second pitch, the first circuit structure comprises a first surface and an opposing second surface, the second circuit structure comprises a third surface and an opposing fourth surface, the third circuit structure comprises a fifth surface and an opposing sixth surface, the first surface is bonded to the third surface, the fourth surface is bonded to the fifth surface, and a direction from the second surface to the sixth surface passes through the first surface, the third surface, the fourth surface, and the fifth surface. ### Claim 40 (depends on 38) The manufacturing method of the semiconductor substrate structure according to claim 38, wherein a coefficient of thermal expansion of the third bonding layer is smaller than a coefficient of thermal expansion of the first bonding layer and a coefficient of thermal expansion of the second bonding layer. ### Claim 41 (depends on 38) The manufacturing method of the semiconductor substrate structure according to claim 38, wherein a dielectric layer in the first circuit structure and a dielectric layer in the second circuit structure are organic thin films. ### Claim 42 (depends on 38) The manufacturing method of the semiconductor substrate structure according to claim 38, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are the same. ### Claim 43 (depends on 38) The manufacturing method of the semiconductor substrate structure according to claim 38, wherein a material of a dielectric layer in the first circuit structure and a material of a dielectric layer in the second circuit structure are different. ### Claim 44 (depends on 38) The manufacturing method of the semiconductor substrate structure according to claim 38, wherein a number of the first circuit layers of the first circuit structure is the same as a number of the second circuit layers of the second circuit structure. ### Claim 45 (depends on 38) The manufacturing method of the semiconductor substrate structure according to claim 38, wherein a number of the first circuit layers of the first circuit structure is different from a number of the second circuit layers of the second circuit structure. ### Claim 46 (depends on 45) The manufacturing method of the semiconductor substrate structure according to claim 45, wherein the number of the first circuit layers of the first circuit structure and the number of the second circuit layers of the second circuit structure are one layer or two layers. ### Claim 47 A manufacturing method of a semiconductor substrate structure, comprising: forming a second circuit structure on a second temporary carrier; forming a third circuit structure on the second circuit structure; bonding the second circuit structure and the third circuit structure; removing the second temporary carrier; forming a first circuit structure on a first temporary carrier; directly bonding the first circuit structure and the second circuit structure; removing the first temporary carrier; and forming a conductive pillar and a conductive cap on a surface of the first circuit structure, and forming an external terminal on a surface of the third circuit structure. ### Claim 48 (depends on 47) The manufacturing method of the semiconductor substrate structure according to claim 47, wherein the third circuit structure is not disposed on a temporary carrier during a manufacturing process and is a plate-like structure with support. ### Claim 49 (depends on 47) The manufacturing method of the semiconductor substrate structure according to claim 47, wherein a dielectric layer in the first circuit structure and a dielectric layer in the second circuit structure are organic thin films.