# US 12,014,881 B2 · High frequency capacitor and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,014,881 B2
- Document ID: US12014881B2
- Status: Granted
- Kind: B2
- Application number: 17/709,338
- Filed: 2022-03-30
- Published: 2022-10-13
- Granted: 2024-06-18
- Earliest claimed: 2021-03-31
- Assignees: Korea Electronics Technology Institute
- Applicants: Korea Electronics Technology Institute
- Inventors: Jong Min Yook; Je In Yu; Jun Chul Kim; Dong Su Kim
- Web page: https://patentgrep.com/patent/US12014881B2

## CPC

- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H01G 4/005: Electrodes
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/385: {Single unit multiple capacitors, e.g. dual capacitor in one coil}
- H10D 1/716: {having vertical extensions}
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.

## Claims

### Claim 1

A high frequency capacitor comprising:
a substrate;
a first opening portion formed in the substrate to pass through the substrate from an upper surface of the substrate to a lower surface of the substrate;
a dielectric layer formed over the first opening portion of the substrate and extended over the substrate around an edge of the first opening portion, wherein the dielectric layer comprises a plurality of trench structures formed on the first opening portion;
a second opening portion formed on the dielectric layer around the edge of the first opening portion;
an upper electrode formed on an upper surface of the dielectric layer and covering the plurality of trench structures;
a pad connecting electrode formed on the second opening portion; and
a lower electrode formed on a lower surface of the dielectric layer and covering the plurality of trench structures and the second opening portion, wherein the lower electrode is contacted with the pad connecting electrode at the second opening portion.

### Claim 2 (depends on 1)

The high frequency capacitor according to claim 1, further comprising:
an insulating layer formed on an upper surface of the upper electrode over the plurality of trench structures;
a first pad formed on the pad connecting electrode and connected to the lower electrode, and configured to contact an external circuit;
a third opening portion formed on the insulating layer around the edge of the first opening portion;
a second pad formed on the third opening portion and connected to the upper electrode at the third opening portion, and configured to contact the external circuit; and
a protective layer formed on a lower surface of the lower electrode.

### Claim 3 (depends on 1)

The high frequency capacitor according to claim 1, wherein the lower electrode has a thickness equal to or greater than a thickness of the upper electrode.

### Claim 4 (depends on 1)

A method for manufacturing the high frequency capacitor according to claim 1, comprising:
preparing the substrate for formation of the capacitor;
forming the dielectric layer at the upper surface of the substrate;
forming the upper electrode at the upper surface of the dielectric layer;
removing at least a portion of the substrate, thereby exposing at least a portion of the lower surface of the dielectric layer; and
forming the lower electrode at the lower surface of the dielectric layer.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the preparing comprises:
preparing the substrate; and
forming a plurality of trenches at one surface of the substrate, for determination of a shape of the dielectric layer.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the preparing comprises a removal region pre-treatment step performed after the forming a plurality of trenches when the substrate is made of a photosensitive glass material, the removal region pre-treatment step performing photosensitization and heat treatment on a portion of the substrate to be removed in the exposing the dielectric layer.

### Claim 7 (depends on 4)

The method according to claim 4, wherein the forming a dielectric layer uses a thermal oxidation process and a chemical vapor deposition process, for formation of the dielectric layer, when the substrate is made of a silicon material, and uses a chemical vapor deposition process, for formation of the dielectric layer, when the substrate is made of a photosensitive glass material.

### Claim 8 (depends on 4)

The method according to claim 4, further comprising:
an insulating layer forming step of forming an insulating layer at an upper surface of the upper electrode, after the forming an upper electrode;
an upper pad forming step of forming a first pad to be connected to the upper surface of the upper electrode and a second pad to be connected to a region where the lower electrode will be formed, after the insulating layer forming step; and
a protective layer forming step of forming a protective layer at a lower surface of the lower electrode, after the lower electrode forming step.

### Claim 9 (depends on 4)

The method according to claim 4, further comprising:
an insulating layer forming step of forming an insulating layer at an upper surface of the upper electrode, after the forming an upper electrode;
a protective layer forming step of forming a protective layer covering the lower electrode, thereby protecting the lower electrode, after the forming a lower electrode; and
a lower pad forming step of forming a first pad to be connected to a lower surface of the upper electrode and a second pad to be connected to a lower surface of the lower electrode, after the protective layer forming step.

### Claim 10 (depends on 4)

The method according to claim 4, wherein the exposing the dielectric layer completely removes the substrate, to expose the lower surface of the dielectric layer.

### Claim 11

A high frequency capacitor comprising:
a dielectric layer comprising a plurality of trench structures;
an upper electrode formed on an upper surface of the dielectric layer and covering and filling the plurality of trench structures;
a opening portion formed on the dielectric layer around an edge of the trench structures, and configured to expose a lower surface of the upper electrode;
a lower electrode formed on a lower surface of the dielectric layer and covering and filling the plurality of trench structures and exposing the opening portion;
an insulating layer formed on an upper surface of the upper electrode over the plurality of trench structures;
a protective layer formed on a lower surface of the lower electrode and covering the dielectric layer and the insulating layer;
a first space formed on the protective layer to expose a portion of the lower surface of the lower electrode;
a second space formed on the protective layer to expose a portion of the lower surface of the upper electrode through the opening portion;
a first pad formed on the first space and connected to the lower surface of the lower electrode, and configured to contact an external circuit; and
a second pad formed on the second space and connected to the lower surface of the upper electrode, and configured to contact an external circuit.