# US 12,014,797 B2 · Apparatuses, systems, and methods for managing metadata storage at a memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,797 B2 - Document ID: US12014797B2 - Status: Granted - Kind: B2 - Application number: 17/731,024 - Filed: 2022-04-27 - Published: 2023-11-02 - Granted: 2024-06-18 - Earliest claimed: 2022-04-27 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sujeet Ayyapureddi - Web page: https://patentgrep.com/patent/US12014797B2 ## CPC - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) - G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 7/1069: {I/O lines read out arrangements} - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 8/10: Decoders - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G06F 2212/1008: Correctness of operation, e.g. memory ordering - G06F 2212/1024: Latency reduction - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during an metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address. ## Claims ### Claim 1 An apparatus comprising: a memory array comprising a plurality of column planes; a column decoder comprising a metadata column address generator, wherein during an metadata access operation, the column decoder is configured to receive a column address derived identifying a particular column to be accessed within each of the plurality of column planes, wherein the metadata column address generator is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of the plurality of column planes, wherein the column decoder is configured to facilitate a double cycle access operation to at least one of write data to and retrieve data from each of the plurality of column planes based on the column address and to at least one of write metadata to and retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the plurality of column planes corresponding to the column plane address. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein for a read operation: during a first cycle of the double access cycle, the column decoder is configured to provide the metadata column address as a first cycle address to the memory array to cause first cycle data to be retrieved from the memory array, wherein the metadata is included in the first cycle data; and during a second cycle of the double access cycle, the column decoder is configured to provide the column address as a second cycle address to the memory array to cause read data to be retrieved from the memory array. ### Claim 3 (depends on 2) The apparatus of claim 2, further comprising a metadata input/output circuit configured to extract the metadata from the first cycle data based on the metadata column plane address and to combine the metadata with the read data received from the second cycle of the double access cycle. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the metadata input/output circuit includes a multiplexer configured to extract the metadata from the first cycle data based on the metadata column address. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the metadata input/output circuit includes a latch circuit configured to store the metadata while read data is being retrieved during the second cycle of the double access cycle. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein for a write operation: during a first cycle of the double access cycle, the column decoder is configured to provide the column address as a first cycle address to the memory array to cause write data to be stored at the memory array; and during a second cycle of the double access cycle, the column decoder is configured to provide the metadata column address to cause second cycle data to be read from the memory array and modified second cycle data to be written to the memory, wherein a selected portion of the second cycle data identified by the metadata column plane address is replaced with the metadata to provide the modified second cycle data. ### Claim 7 (depends on 6) The apparatus of claim 6, further comprising a metadata input/output circuit configured to receive the write data and the metadata, and to extract the metadata from the write data, wherein the metadata input/output circuit is further configured to replace the selection portion of the second cycle data with the metadata based on the metadata column plane address. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the metadata input/output circuit includes a read-modify-write circuit configured to replace the selected portion of the second cycle data identified based on the metadata column plane address with the metadata. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the metadata input/output circuit includes an extraction circuit configured to extract the write data and the metadata from data received via a data bus, wherein the extraction circuit is configured to provide the write data to the memory array. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the metadata input/output circuit includes a latch circuit configured to receive the metadata from the extraction circuit and store the metadata while the second cycle data is being retrieved during the second cycle of the double access cycle. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the metadata column address generator is configured to decode 4 or fewer of the least significant bits of the column address to determine the metadata column address and the metadata column plane address corresponding to the particular one of the plurality of column planes. ### Claim 12 A method comprising: during a read operation at a memory to retrieve read data and metadata associated with a column address: decoding a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of a plurality of column planes of a memory array of the memory; during a first cycle of a double access cycle, providing the metadata column address as a first cycle address to the memory array to cause first cycle data to be retrieved from the memory array, wherein the metadata is included in the first cycle data; and during a second cycle of the double access cycle, providing the column address as a second cycle address to the memory array to cause the read data to be retrieved from the memory array. ### Claim 13 (depends on 12) The method of claim 12, further comprising extracting the metadata from the first cycle data based on the metadata column plane address. ### Claim 14 (depends on 13) The method of claim 13, further comprising combining the read data and the metadata for provision to a data bus. ### Claim 15 (depends on 13) The method of claim 13, further comprising latching the metadata while read data is being retrieved during the second cycle of the double access cycle. ### Claim 16 (depends on 12) The method of claim 12, further comprising determining the metadata column plane address based on a least significant bit of the column address. ### Claim 17 (depends on 12) The method of claim 12, further comprising determining the metadata column plane address based on 3 or 4 least significant bits of the column address. ### Claim 18 (depends on 12) The method of claim 12, further comprising determining the metadata column plane address based on a combination of a subset of least significant bits of the column address and another column address. ### Claim 19 A method comprising: during a write operation at a memory to store write data and metadata associated with a column address: decoding a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of a plurality of column planes of a memory array of the memory; during a first cycle of a double access cycle, providing the column address as a first cycle address to the memory array to cause write data to be stored at the memory array; and during a second cycle of the double access cycle, performing a read-modify-write operation by providing the metadata column address to the memory array to cause second cycle data to be read from the memory array, a selected portion thereof identified by the metadata column plane address to be modified with the metadata, and to be written back to the memory array at the metadata column address. ### Claim 20 (depends on 19) The method of claim 19, further comprising: receiving bus data that includes both the write data and the metadata; and extracting the metadata from the bus data. ### Claim 21 (depends on 20) The method of claim 20, further comprising replacing the selected portion of the second cycle data identified based on the metadata column plane address with the metadata. ### Claim 22 (depends on 20) The method of claim 20, further comprising latching the extracted metadata during the first cycle of the double access cycle. ### Claim 23 (depends on 19) The method of claim 19, further comprising determining the metadata column plane address based on a least significant bit of the column address. ### Claim 24 (depends on 19) The method of claim 19, further comprising determining the metadata column plane address based on 3 or 4 least significant bits of the column address. ### Claim 25 (depends on 19) The method of claim 19, further comprising determining the metadata column plane address based on a combination of a subset of least significant bits of the column address and another column address. ### Claim 26 (depends on 19) The method of claim 19, further comprising determining which bits of the column address to use to decode based on a system architecture of the memory.