# US 12,014,796 B2 · Memory device and method of operating the same

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- Number: US 12,014,796 B2
- Document ID: US12014796B2
- Status: Granted
- Kind: B2
- Application number: 17/669,628
- Filed: 2022-02-11
- Published: 2023-08-17
- Granted: 2024-06-18
- Earliest claimed: 2022-02-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Meng-Sheng Chang; Ku-Feng Lin
- Web page: https://patentgrep.com/patent/US12014796B2

## CPC

- G11C 7/08: Control thereof
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

## Claims

### Claim 1

A memory device, comprising:
a plurality of memory cells including a first memory cell and a second memory cell, wherein the first and second memory cells share a first word line transistor;
a first bit line connected to the first memory cell;
a second bit line connected to the second memory cell;
a first word line connected to the first word line transistor shared by the first and second memory cells;
a first control transistor connected to the first bit line;
a second control transistor connected to second bit line;
a first mux transistor commonly connected to the first and second control transistors; and
a sense amplifier connected to the first mux transistor.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first and second control transistors each has a gate terminal connected to a common gate control line.

### Claim 3 (depends on 2)

The memory device of claim 2, further comprising a controller, during a read operation of the first memory cell connected to the first word line, configured to:
activate the first word line;
activate the common gate control line; and
activate a mux control line connected to a gate terminal of the first mux transistor.

### Claim 4 (depends on 3)

The memory device of claim 3, further comprising a third control transistor connected to the first and second control transistors and ground.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the controller, during the read operation, is further configured to deactivate a control line connected to a gate terminal of the third control transistor.

### Claim 6 (depends on 5)

The memory device of claim 5, further comprising a second word line connected to third and fourth memory cells of the plurality of memory cells.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the controller is configured to, during the read operation, deactivate the second word line.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the plurality of memory cells each comprise a storage unit including a resistor or a capacitor.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the first word line is connected to an M number of the plurality of memory cells, and the sense amplifier is connected to an N number of mux transistors including the first mux transistor, where M and N are positive integers.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein a number of a plurality of control transistors, including the first and second control transistors, connected to a common gate line and a plurality of bit lines, including the first and second bit lines, connected to the mux transistor are equal to M.

### Claim 11

A method of operating a memory device, comprising:
activating, during a read operation of a first memory cell, a first word line connected to a first word line transistor shared by the first memory cell and a second memory cell;
activating a first control gate line connected to the first memory cell;
activating a mux control line connected to a mux transistor, the mux transistor connected to a sense amplifier; and
activating a common gate signal line connected to a gate terminal of a first common gate transistor connected to the first memory cell and a gate terminal of a second common gate transistor connected to the second memory cell.

### Claim 12 (depends on 11)

The method of claim 11, further comprising deactivating a second word line connected to a second word line transistor shared by a third memory cell and a fourth memory cell, wherein the second word line transistor having has (i) a drain terminal connected to a first control gate transistor of the third memory cell and a second control gate transistor of the fourth memory cell and Iii) a source terminal connected to the ground.

### Claim 13 (depends on 11)

The method of claim 11, further comprising deactivating a second control gate line connected to the second memory cell.

### Claim 14 (depends on 11)

The method of claim 11, wherein the memory cell includes a storage unit including a resistor or a capacitor.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first and second common gate transistors, the mux transistor, and a control transistor are connected to one another at a node.

### Claim 16

A memory system, comprising:
a plurality of memory cells including a first memory cell and a second memory cell, wherein the first and second memory cells share a first word line transistor;
a sense amplifier connected to the plurality of memory cells via a plurality of bit lines; and
a controller connected to the plurality of memory cells, wherein the controller is configured to:
activate, during a read operation of a first memory cell, a first word line connected to the first word line transistor shared by the first memory cell and a second memory cell;
activate a first control gate line connected to the first memory cell;
activate a mux control line connected to a mux transistor, the mux transistor connected to a sense amplifier; and
activate a common gate signal line connected to a gate terminal of a first common gate transistor connected to the first memory cell and a gate terminal of a second common gate transistor connected to the second memory cell.

### Claim 17 (depends on 16)

The memory system of claim 16, wherein the controller is further configured to deactivate a second word line connected to a second word line transistor shared by a third memory cell and a fourth memory cell, wherein the second word line transistor has (i) a drain terminal connected to the first control gate transistor of the third memory cell and a second control gate transistor of the fourth memory cell and cii) a source terminal connected to the ground.

### Claim 18 (depends on 16)

The memory system of claim 16, wherein the controller is further configured to deactivate a second control gate line connected to the second memory cell.

### Claim 19 (depends on 16)

The memory system of claim 16, wherein the plurality of memory cells each include a storage unit including a resistor or a capacitor.

### Claim 20 (depends on 16)

The memory system of claim 16, wherein the first and second common gate transistors, the mux transistor, and a control transistor are connected to one another at a node.