# US 12,014,795 B2 · Double sense amp and fractional bit assignment in non-volatile memory structures

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- Number: US 12,014,795 B2
- Document ID: US12014795B2
- Status: Granted
- Kind: B2
- Application number: 17/486,090
- Filed: 2021-09-27
- Published: 2023-04-13
- Granted: 2024-06-18
- Earliest claimed: 2021-09-27
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Yuki Fujita; Kei Kitamura; Kyosuke Matsumoto; Masahiro Kano; Minoru Yamashita; Ryuji Yamashita; Shuzo Otsuka
- Web page: https://patentgrep.com/patent/US12014795B2

## CPC

- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 16/10: Programming or data input circuits
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.

## Claims

### Claim 1

A method for programming a non-volatile memory structure, comprising:
initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, the memory structure comprising:
a first memory array corresponding to a floor of the memory structure, the first memory array comprising a first population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the first memory array is disposed below the first population of the plurality of memory cells;
a second memory array corresponding to a ceiling of the memory structure and:
electrically coupled to and interconnected with the first memory array via a continuous communication pathway such that the first memory array and the second memory array operate as a contiguous memory device;
vertically inverted relative to and positioned on top of the first memory array; and
comprising a second population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the second memory array is disposed above the second population of the plurality of memory cells; and
a data bus tap electrically coupling the first memory array and to the second memory array.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first memory array and the second memory array are of the “CMOS Under the Array” architecture type.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the two-dimensional fractional number of bits-per-cell programming scheme is an “n.5” bits-per-cell programming scheme, wherein “n” is any integer.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising initiating a read memory operation wherein:
a first read level is applied to the first memory cell; and
a second read level is applied to the second memory cell.

### Claim 5 (depends on 1)

The method according to claim 1, wherein:
the first memory array comprises a first bit line data bus;
the second memory array comprises a second bit line data bus; and
the data bus tap electrically couples the first bit line data bus and the second bit line data bus.

### Claim 6

A memory controller, comprising:
a first communication pathway configured to couple to a non-volatile memory structure; and
the memory controller configured to:
initiate a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, the memory structure comprising:
a first memory array corresponding to a floor of the memory structure, the first memory array comprising a first population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the first memory array is disposed below the first population of the plurality of memory cells;
a second memory array corresponding to a ceiling of the memory structure and:
electrically coupled to and interconnected with the first memory array via a continuous communication pathway such that the first memory array and the second memory array operate as a contiguous memory device;
vertically inverted relative to and positioned on top of the first memory array; and
comprising a second population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the second memory array is disposed above the second population of the plurality of memory cells; and
a data bus tap electrically coupling the first memory array and to the second memory array.

### Claim 7 (depends on 6)

The memory controller according to claim 6, wherein the first memory array and the second memory array are of the “CMOS Under the Array” architecture type.

### Claim 8 (depends on 6)

The memory controller according to claim 6, wherein the two-dimensional fractional number of bits-per-cell programming scheme is an “n.5” bits-per-cell programming scheme, wherein “n” is any integer.

### Claim 9 (depends on 6)

The memory controller according to claim 6, wherein the memory controller is further configured to initiate a read memory operation in which:
a first read level is applied to the first memory cell; and
a second read level is applied to the second memory cell.

### Claim 10 (depends on 6)

The memory controller according to claim 6, wherein:
the first memory array comprises a first bit line data bus;
the second memory array comprises a second bit line data bus; and
the data bus tap electrically couples the first bit line data bus and the second bit line data bus.

### Claim 11 (depends on 6)

The memory controller according to claim 6, wherein data mapping circuitry of the memory structure is utilized to perform the two-dimensional fractional number of bits-per-cell programming scheme.

### Claim 12

A non-volatile memory system, comprising:
a memory structure, comprising:
a first memory array corresponding to a floor of the memory structure, the first memory array comprising a first population of a plurality of memory cells of the memory structure and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the first memory array is disposed below the first population of the plurality of memory cells;
a second memory array corresponding to a ceiling of the memory structure and:
electrically coupled to and interconnected with the first memory array via a continuous communication pathway such that the first memory array and the second memory array operate as a contiguous memory device;
vertically inverted relative to and positioned on top of the first memory array; and
comprising a second population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the second memory array is disposed above the second population of the plurality of memory cells; and
a data bus tap electrically coupling the first memory array and the second memory array; and
a memory controller coupled to the memory structure and initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of the plurality of memory cells of the memory structure.

### Claim 13 (depends on 12)

The non-volatile memory system according to claim 12, wherein the first memory array and the second memory array are of the “CMOS Under the Array” architecture type.

### Claim 14 (depends on 12)

The non-volatile memory system according to claim 12, wherein the two-dimensional fractional number of bits-per-cell programming scheme is an “n.5” bits-per-cell programming scheme, wherein “n” is any integer.

### Claim 15 (depends on 12)

The non-volatile memory system according to claim 12, further comprising the memory controller initiating a read memory operation in which:
a first read level is applied to the first memory cell; and
a second read level is applied to the second memory cell.

### Claim 16 (depends on 12)

The non-volatile memory system according to claim 12, wherein:
the first memory array comprises a first bit line data bus;
the second memory array comprises a second bit line data bus; and
the data bus tap electrically couples the first bit line data bus and the second bit line data bus.

### Claim 17 (depends on 12)

The non-volatile memory system according to claim 12, wherein data mapping circuitry of the memory structure is utilized to perform the two-dimensional fractional number of bits-per-cell programming scheme.