# US 12,014,792 B2 · Monitoring and adjusting access operations at a memory device

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- Number: US 12,014,792 B2
- Document ID: US12014792B2
- Status: Granted
- Kind: B2
- Application number: 18/108,302
- Filed: 2023-02-10
- Published: 2023-06-22
- Granted: 2024-06-18
- Earliest claimed: 2020-07-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Mark D. Ingram; Todd Jackson Plum; Scott E. Schaefer; Aaron P. Boehm; Scott D. Van De Graaff
- Web page: https://patentgrep.com/patent/US12014792B2

## CPC

- G11C 29/4401: {for self repair}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G11C 29/021: {in voltage or current generators}
- G11C 29/022: {in I/O circuitry}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/026: {in sense amplifiers}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/12005: {comprising voltage or current generators}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/81: {using a hierarchical redundancy scheme}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7206: Reconfiguration of flash memory system
- G06F 2212/7211: Wear leveling
- G11C 2029/0409: {Online test}
- G11C 2207/2254: Calibration
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

## Claims

### Claim 1

A method, comprising:
monitoring, over a plurality of access operations of a memory device, a metric related to an access operation for the memory device;
transmitting, to a source external to the memory device and according to a configuration for managing access to the memory device, an indication of the metric; and
determining whether to adjust a parameter associated with performing access operations received by the memory device based at least in part on the metric satisfying a threshold, the configuration for managing access to the memory device, and an indication to adjust the parameter associated with performing access operations from the source external to the memory device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
receiving, from the source external to the memory device, the indication to adjust the parameter associated with performing access operations received by the memory device.

### Claim 3 (depends on 1)

The method of claim 1, wherein the metric represents a repeated access pattern of the memory device over the plurality of access operations.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
modifying a mapping for the memory device based at least in part on determining whether to adjust the parameter associated with performing access operations received by the memory device.

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
modifying one or more parameters associated with the memory device based at least in part on determining whether to adjust the parameter associated with performing access operations received by the memory device.

### Claim 6 (depends on 1)

The method of claim 1, wherein the metric indicates a degradation in performance of a component of the memory device.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
modifying one or more parameters associated with the component of the memory device based at least in part on determining whether to adjust the parameter associated with performing access operations received by the memory device.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
triggering a recalibration of the component based at least in part on determining whether to adjust the parameter associated with performing access operations received by the memory device.

### Claim 9 (depends on 1)

The method of claim 1, wherein the metric represents a level of wear of a component of the memory device.

### Claim 10 (depends on 1)

The method of claim 1, wherein the configuration comprises a monitoring configuration, the method further comprising:
receiving the monitoring configuration comprising an indication to report the metric related to the access operation for the memory device, wherein transmitting the indication of the metric is based at least in part on receiving the monitoring configuration.

### Claim 11

A memory device, comprising:
one or more registers configured to store a configuration for managing access to the memory device; and
circuitry configured to:
monitor, over a plurality of access operations of the memory device, a metric related to an access operation for the memory device;
transmit, to a source external to the memory device and according to the configuration for managing access to the memory device, an indication of the metric; and
determine whether to adjust a parameter associated with performing access operations received by the memory device based at least in part on the configuration for managing access to the memory device, the metric satisfying a threshold, and an indication to adjust the parameter associated with performing access operations from the source external to the memory device.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the circuitry is further configured to:
receive, from the source external to the memory device, the indication to adjust the parameter associated with performing access operations received by the memory device.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the circuitry is further configured to:
modify a mapping for a component of the memory device based at least in part on determining whether to adjust the parameter associated with performing access operations received by the memory device.

### Claim 14 (depends on 11)

The memory device of claim 11, wherein the configuration comprises a monitoring configuration, wherein the circuitry is further configured to:
receive a monitoring configuration comprising an indication to report the metric related to the access operation for the memory device, wherein transmitting the indication of the metric is based at least in part on receiving the monitoring configuration.

### Claim 15

An apparatus, comprising:
one or more memory arrays;
a monitoring circuit configured to:
monitor, over a plurality of access operations of the one or more memory arrays, a metric related to an access operation for the one or more memory arrays; and
determine that the metric satisfies a threshold; and
a corrective circuit configured to:
adjust a parameter associated with performing access operations received by the one or more memory arrays based at least in part on a configuration for managing access to the one or more memory arrays, determining that the metric satisfying the threshold, and an indication to adjust the parameter associated with performing access operations.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein, to adjust the parameter associated with performing the access operations received by the one or more memory arrays, the corrective circuit is configured to:
modify a row address term, adjust a sense amplifier control voltage or timing, adjust an internal voltage for a component of the one or more memory arrays, adjust an output impedance trim, perform a recalibration procedure for a component of the one or more memory arrays, or a combination thereof.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein, to determine that the metric satisfies the threshold, the monitoring circuit is configured to:
identify that an address pattern or a level of wear associated with the one or more memory arrays satisfies the threshold.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the corrective circuit is configured to:
receive, from a source external to the apparatus, indication to adjust the parameter associated with performing the access operations received by the one or more memory arrays, wherein adjusting the parameter associated with performing the access operations received by the one or more memory arrays is based at least in part on receiving the indication.

### Claim 19 (depends on 15)

The apparatus of claim 15, wherein the corrective circuit is a subcomponent of the monitoring circuit.

### Claim 20 (depends on 15)

The apparatus of claim 15, further comprising:
a traffic monitor coupled with the one or more memory arrays and configured to:
detect the plurality of access operations of the one or more memory arrays; and
a sensor configured to:
detect a level of wear or degradation for a component of the one or more memory arrays, wherein the corrective circuit is configured to adjust the parameter associated with performing the access operations received by the one or more memory arrays based at least in part on the sensor detecting the level of wear or degradation for the component of the one or more memory arrays.