# US 12,014,788 B2 · Memory array detection circuit and detection method, and memory

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- Number: US 12,014,788 B2
- Document ID: US12014788B2
- Status: Granted
- Kind: B2
- Application number: 17/813,597
- Filed: 2022-07-19
- Published: 2023-11-02
- Granted: 2024-06-18
- Earliest claimed: 2022-04-29
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Weijie Cheng; Onegyun Na; Liuyan Hong
- Web page: https://patentgrep.com/patent/US12014788B2

## CPC

- G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals}
- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/36: Data generation devices, e.g. data inverters
- G11C 29/38: Response verification devices
- G11C 29/40: using compression techniques
- G11C 2029/0401: {in embedded memories}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory array detection circuit includes: a memory array including multiple memory cells; a write circuit, connected to the memory array and configured to write same initial data into each memory cell of the memory array; a read circuit, connected to the memory array and configured read the data stored in each memory cell of the memory array; and a data compression circuit, connected to the read circuit and configured to: compare the data read from the multiple memory cells, and detect whether the memory array is defective according to whether the read data are identical.

## Claims

### Claim 1

A memory array detection circuit, comprising:
a memory array comprising multiple memory cells;
a write circuit, connected to the memory array and configured to write same initial data into each memory cell of the memory array;
a read circuit, connected to the memory array and configured to read data stored in each memory cell of the memory array; and
a data compression circuit, connected to the read circuit and configured to: compare data read from the multiple memory cells, and detect whether the memory array is defective according to whether the read data are identical;
wherein the memory array detection circuit further comprises: a data transmission interface through which the stored data is read, wherein the data transmission interface comprises at least four transmission sub-interfaces; and the memory array comprises multiple memory matrixes, each of the multiple memory matrixes comprises multiple memory sub-arrays, and each of the multiple memory sub-arrays comprises multiple memory cells, wherein all memory sub-arrays of the memory array are divided into at least four memory sub-array groups electrically connected to the at least four transmission sub-interfaces in one-to-one correspondence; wherein the data compression circuit comprises a first data compression circuit and a second data compression circuit; the first data compression circuit is connected to the read circuit, and is configured to determine, for each of the at least four transmission sub-interfaces, whether data of multiple memory cells output by the transmission sub-interface are identical; and the second data compression circuit is connected to the first data compression circuit, and is configured to determine whether data output by each two of the at least four transmission sub-interfaces is identical;
or
wherein the memory array detection circuit further comprises: a data transmission interface through which the stored data is read, wherein the data transmission interface comprises at least four first transmission sub-interfaces, and each first transmission sub-interface comprises at least four second transmission sub-interfaces; and the memory array comprises multiple memory matrixes that are divided into at least four memory matrix groups electrically connected to the at least four first transmission sub-interfaces in one-to-one correspondence; each of the multiple memory matrixes comprises multiple memory sub-arrays, and each of the multiple memory sub-arrays comprises multiple memory cells; and multiple memory sub-arrays in each of the multiple memory matrixes are divided into at least four memory sub-array groups electrically connected to corresponding second transmission sub-interfaces in one-to-one correspondence; wherein the data compression circuit comprises a first data compression circuit and a second data compression circuit; the first data compression circuit is connected to the read circuit and is configured to: obtain, through each of the at least four first transmission sub-interfaces, data output by all corresponding second transmission sub-interfaces, and determine, for each of the corresponding second transmission sub-interfaces, whether data output by the second transmission sub-interface are identical; and the second data compression circuit is connected to the first data compression circuit and is configured to determine whether data output by each two of the at least two second transmission sub-interfaces are identical.

### Claim 2 (depends on 1)

The memory array detection circuit of claim 1, further comprising:
an output circuit, connected to the first data compression circuit and the second data compression circuit, and configured to output three states according to determination results of the first data compression circuit and the second data compression circuit.

### Claim 3 (depends on 1)

The memory array detection circuit of claim 1, further comprising:
a locating circuit, configured to locate and mark a defective memory cell in response to that the memory array is defective.

### Claim 4 (depends on 1)

A memory, comprising the memory array detection circuit of claim 1.

### Claim 5

A memory array detection method, comprising:
writing, by a write circuit, same initial data into each memory cell of the memory array;
reading, by a read circuit, data stored in each memory cell of the memory array;
comparing, by a data compression circuit, data read from memory cells of the memory array, and detecting whether the memory array is defective according to whether the read data are identical;
wherein the memory array comprises multiple memory matrixes, each of the multiple memory matrixes comprises multiple memory sub-arrays, and each of the multiple memory sub-arrays comprises multiple memory cells; all memory sub-arrays in the memory array are divided into at least four memory sub-array groups, data in memory cells corresponding to each of the at least four memory sub-array groups are output through a same transmission sub-interface, and a number of transmission sub-interfaces is identical to a number of the at least four memory sub-array groups;
wherein the data compression circuit comprises a first data compression circuit and a second data compression circuit, and the method further comprises:
comparing, by the first data compression circuit for each of the transmission sub-interfaces, data output by the transmission sub-interface to determine whether data in multiple memory cells output by the transmission sub-interface are identical;
in response to that the data in the multiple memory cells output by the transmission sub-interface are not identical, determining that the memory array is defective;
in response to that the data in the multiple memory cells output by each of the transmission sub-interfaces are identical, performing further comparison by the second data compression circuit by: for each two of the transmission sub-interfaces, comparing data output by the two of the transmission sub-interfaces to determine whether the data output by the two of the transmission sub-interfaces are identical;
in response to that the data output by the two of the transmission sub-interfaces are not identical, determining that the memory array is defective; and
in response to that the data output by each two of the transmission sub-interfaces are identical and the output data are identical to the initial data, determining that the memory array is not defective.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
in response to that the first data compression circuit determines that data in multiple memory cells are not identical, outputting, by an output circuit, a high-impedance state;
in response to that the second data compression circuit determines that data in multiple memory cells are not identical, outputting, by the output circuit, “0”; and
in response to that the second data compression circuit determines that data in multiple memory cells are identical and are identical to the initial data, outputting, by the output circuit, “1”.

### Claim 7 (depends on 5)

The method of claim 5, further comprising:
in response to that the memory array is defective, locates and marks, by a locating circuit, a defective memory cell.

### Claim 8

A memory array detection method, comprising:
writing, by a write circuit, same initial data into each memory cell of the memory array;
reading, by a read circuit, data stored in each memory cell of the memory array;
comparing, by a data compression circuit, data read from memory cells of the memory array, and detecting whether the memory array is defective according to whether the read data are identical;
wherein the memory array comprises multiple memory matrixes that are divided into at least four memory matrix groups, each of the at least four memory matrix groups outputs data through a respective first transmission sub-interface, a number of first transmission sub-interfaces is identical to a number of the at least four memory matrix groups; and
each of the multiple memory matrixes comprises multiple memory sub-arrays, and each of the multiple memory sub-arrays comprises multiple memory cells; the multiple memory sub-arrays in each of the multiple memory matrixes are divided into at least four memory sub-array groups that output data through second transmission sub-interfaces respectively, and the second transmission sub-interfaces are in one-to-one correspondence to the at least four memory sub-array groups;
wherein the data compression circuit comprises a first data compression circuit and a second data compression circuit, and the method further comprises:
operation a) acquiring, for a first memory matrix group through a corresponding first transmission sub-interface by the first data compression circuit, data output by all corresponding second transmission sub-interfaces, and determining, for each of the corresponding second transmission sub-interfaces, whether data of multiple memory cells output by the second transmission sub-interface are identical;
operation b) in response to that the data of the multiple memory cells output by the second transmission sub-interface are not identical, determining that the first memory matrix group is defective;
operation c) in response to that the data of the multiple memory cells output by each of the corresponding second transmission sub-interfaces are identical, performing further comparison by the second data compression circuit by: comparing data output by each two of the corresponding second transmission sub-interfaces to determine whether the data output by the two of the corresponding second transmission sub-interfaces are identical;
operation d) in response to that the data output by the two of the corresponding second transmission sub-interfaces are not identical, determining that the first memory matrix is defective;
operation e) in response to that the data output by each two of the corresponding second transmission sub-interfaces are identical and the output data are identical to the initial data, determining that the first memory matrix is not defective;
performing same operations a) to e) for remaining memory matrixes in the memory array other than the first memory matrix;
operation f) in response to that data in memory cells of all memory matrixes of the memory array are identical and the output data are identical to the initial data, determining that the memory array is not defective.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
in response to that the first data compression circuit determines that data in multiple memory cells are not identical, outputting, by an output circuit, a high-impedance state;
in response to that the second data compression circuit determines that data in multiple memory cells are not identical, outputting, by the output circuit, “0”; and
in response to that the second data compression circuit determines that data in multiple memory cells are identical and are identical to the initial data, outputting, by the output circuit, “1”.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
in response to that the memory array is defective, locates and marks, by a locating circuit, a defective memory cell.