# US 12,014,784 B2 · Evaluation of background leakage to select write voltage in memory devices

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- Number: US 12,014,784 B2
- Document ID: US12014784B2
- Status: Granted
- Kind: B2
- Application number: 17/845,174
- Filed: 2022-06-21
- Published: 2022-10-06
- Granted: 2024-06-18
- Earliest claimed: 2021-02-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Nevil N. Gajera; Karthik Sarpatwari; Zhongyuan Lu
- Web page: https://patentgrep.com/patent/US12014784B2

## CPC

- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/30: Power supply circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0076: {Write operation performed depending on read result}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2213/35: Material including carbon, e.g. graphite, grapheme
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

## Claims

### Claim 1

A device comprising:
a memory array including a memory cell;
at least one voltage driver configured to drive a first write voltage or a second write voltage on the memory cell, wherein the second write voltage has a greater magnitude than the first write voltage; and
at least one current sensor configured to sense a first current associated with background leakage in the memory array.

### Claim 2 (depends on 1)

The device of claim 1, wherein the characteristic is a current, and further comprising a controller configured to determine that the characteristic is greater than a threshold.

### Claim 3 (depends on 1)

The device of claim 1, further comprising a controller configured to perform a pre-sensing step when performing a write operation on the memory cell.

### Claim 4 (depends on 3)

The device of claim 3, wherein the controller is further configured to evaluate the background leakage based on the pre-sensing step.

### Claim 5 (depends on 1)

The device of claim 1, wherein the memory cell is a target memory cell to be programmed, and the background leakage is caused by memory cells of the memory array other than the target memory cell.

### Claim 6 (depends on 1)

The device of claim 1, further comprising a controller, wherein
the controller is configured to select the first or second write voltage in response to determining that the first current exceeds a first threshold, and a second current associated with a logic state of the memory cell is below a second threshold.

### Claim 7 (depends on 1)

The device of claim 1, wherein the memory cell is a first memory cell, and further comprising a controller configured to:
receive a write command from a host device; and
in response to receiving the write command, cause the voltage driver to apply a pre-sensing voltage to memory cells of the memory array including the first memory cell;
wherein the characteristic is sensed after applying the pre-sensing voltage.

### Claim 8 (depends on 1)

The device of claim 1, further comprising a controller configured to select, based on the sensed first current, the first or second write voltage to drive on the memory cell.

### Claim 9 (depends on 1)

The device of claim 1, further comprising a controller configured to:
receive a write command from a host device;
in response to receiving the write command, cause the voltage driver to apply a pre-read voltage to the memory cell to determine a first logic state of the memory cell; and
determine that the write command corresponds to a second logic state of the memory cell that is different from the first logic state;
wherein the memory cell is programmed to the second logic state using the selected first or second write voltage.

### Claim 10 (depends on 1)

The device of claim 1, further comprising a bit line and a word line, wherein the voltage driver is configured to drive the selected first or second write voltage on the memory cell by applying voltages to the bit line and word line.

### Claim 11 (depends on 1)

The device of claim 1, wherein the first write voltage is a default or normal write voltage, and the second write voltage is a boosted write voltage.

### Claim 12 (depends on 1)

The device of claim 1, further comprising a controller configured to:
apply a pre-sensing voltage, wherein the pre-sensing voltage is applied to sense the characteristic associated with the background leakage; and
apply a pre-read voltage, wherein the pre-read voltage is applied to determine an existing logic state of the memory cell.

### Claim 13

An apparatus comprising:
a memory array including memory cells;
sensing circuitry configured to sense a current; and
a controller configured to:
evaluate background leakage by determining whether the current exceeds a threshold, and in response to determining that the current exceeds the threshold, boost at least one write voltage.

### Claim 14 (depends on 13)

The apparatus of claim 13, further comprising:
bias circuitry configured to apply a pre-read voltage to a first memory cell;
wherein the controller is further configured to determine, based on applying the pre-read voltage, a logic state of the first memory cell.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the current is a first current, and the sensing circuitry is further configured to sense a second current that results from applying the pre-read voltage.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the threshold is a first threshold, and the sensing circuitry is further configured to determine whether the second current is less than a second threshold.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein a write voltage is boosted in response to determining that the second current is less than the second threshold.

### Claim 18 (depends on 13)

The apparatus of claim 13, wherein the controller is further configured to, in response to determining that the current exceeds the threshold, boost the at least one write voltage applied to a first memory cell.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the controller is further configured to apply the boosted write voltage to the first memory cell to change a threshold voltage of the first memory cell.

### Claim 20

A method comprising:
sensing a first current associated with background leakage in a memory array;
selecting, based on the sensed first current, a first write voltage or a second write voltage; and
applying the selected first or second write voltage to a memory cell.