# US 12,014,782 B2 · Memory device for adjusting magnitude of signal used to precharge bit line according to position of plug hole and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,782 B2 - Document ID: US12014782B2 - Status: Granted - Kind: B2 - Application number: 17/561,228 - Filed: 2021-12-23 - Published: 2022-12-08 - Granted: 2024-06-18 - Earliest claimed: 2021-06-02 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jung Hyeong Kim - Web page: https://patentgrep.com/patent/US12014782B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/30: Power supply circuits - H10B 43/10: characterised by the top-view layout - H10B 43/40: characterised by the peripheral circuit region - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory device includes a memory block to which a plurality of lines are connected. The memory device also includes a plurality of memory cells respectively connected to word lines among the plurality of lines, wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit. The memory device further includes a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines. The memory device additionally includes a peripheral circuit for performing a read operation on the plurality of memory cells. The peripheral circuit includes a voltage generator configured to control a signal applied to the plurality of page buffers so that the read operation is performed according to positions of the plug holes. ## Claims ### Claim 1 A memory device including a memory block to which a plurality of lines are connected, the memory device comprising: a plurality of memory cells respectively connected to word lines among the plurality of lines, wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit; a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines; and a peripheral circuit configured to perform a read operation on memory cells of a first plug hole among the plurality of plug holes, wherein the first plug hole includes at least two memory cells among the plurality of memory cells, and is connected to at least two bit lines among the plurality of bit lines, wherein the peripheral circuit includes a voltage generator which is, during the read operation, configured to adjust a magnitude of a signal applied to at least two page buffers corresponding to the at least two bit lines among the plurality of page buffers to precharge the at least two bit lines according to a position of the first plug hole. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the voltage generator is capable of controlling the magnitude of a signal applied to a first transistor connected to each of the at least two bit lines among transistors included in each of the at least two page buffers according to the position of the first plug hole. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the peripheral circuit is configured to perform the read operation on the first plug hole adjacent to the drain select line among the plurality of plug holes. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the voltage generator is capable of increasing the magnitude of a signal applied to the first transistor as the first plug hole is more adjacent to the drain select line. ### Claim 5 (depends on 3) The memory device of claim 3, wherein the voltage generator is capable of decreasing the magnitude of a signal applied to the first transistor as the first plug hole is more adjacent to the drain select line. ### Claim 6 (depends on 3) The memory device of claim 3, wherein the peripheral circuit is configured to perform the read operation on the first plug hole adjacent to the drain select line, and then perform the read operation on a second plug hole adjacent to the slit. ### Claim 7 (depends on 2) The memory device of claim 2, wherein the peripheral circuit is configured to perform the read operation on the first plug hole adjacent to the slit among the plurality of plug holes. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the voltage generator is capable of increasing the magnitude of a signal applied to the first transistor as the first plug hole is more adjacent to the drain select line. ### Claim 9 (depends on 7) The memory device of claim 7, wherein the voltage generator is capable of decreasing the magnitude of a signal applied to the first transistor as the first plug hole is more adjacent to the drain select line. ### Claim 10 (depends on 7) The memory device of claim 7, wherein the peripheral circuit is configured to perform the read operation on the first plug hole adjacent to the slit and then perform the read operation on a second plug hole adjacent to the drain select line. ### Claim 11 A method for operating a memory device including a memory block to which a plurality of lines are connected, wherein the memory block includes a plurality of memory cells respectively connected to word lines among the plurality of lines and a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines, and wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit, the method comprising: generating a plurality of plug hole groups according to positions of the plurality of plug holes; determining a first plug hole group including at least two memory cells among the plurality of memory cells, and connected to at least two bit lines among the plurality of bit lines; and adjusting, in the read operation on the first plug hole group, a magnitude of a signal applied to at least two page buffers corresponding to the at least two bit lines among a plurality of page buffers to precharge the at least two bit lines according to a position of the first plug hole group. ### Claim 12 (depends on 11) The method of claim 11, wherein adjusting the magnitude of the signal comprises controlling the magnitude of a signal applied to a first transistor connected to each of the at least two bit lines among transistors included in each of the at least two page buffers. ### Claim 13 (depends on 12) The method of claim 12, wherein the read operation is performed on the first plug hole group adjacent to the drain select line among the plurality of plug hole groups. ### Claim 14 (depends on 13) The method of claim 13, wherein adjusting the magnitude of the signal comprises increasing the magnitude of a signal applied to the first transistor as the first plug hole group is more adjacent to the drain select line. ### Claim 15 (depends on 13) The method of claim 13, wherein adjusting the magnitude of the signal comprises decreasing the magnitude of a signal applied to the first transistor as the first plug hole group is more adjacent to the drain select line. ### Claim 16 (depends on 13) The method of claim 13, wherein after the read operation is performed on the first plug hole group adjacent to the drain select line, the read operation is performed on second plug hole group adjacent to the slit. ### Claim 17 (depends on 12) The method of claim 12, wherein the read operation is performed on the first plug hole group adjacent to the slit among the plurality of plug holes. ### Claim 18 (depends on 17) The method of claim 17, wherein adjusting the magnitude of the signal comprises increasing the magnitude of a signal applied to the first transistor as the first plug hole group is more adjacent to the drain select line. ### Claim 19 (depends on 17) The method of claim 17, wherein adjusting the magnitude of the signal comprises decreasing the magnitude of a signal applied to the first transistor as the first plug hole group is more adjacent to the drain select line. ### Claim 20 (depends on 17) The method of claim 17, wherein, after the read operation is performed on the first plug hole group adjacent to the slit, the read operation is performed on a second plug hole group adjacent to the drain select line.