# US 12,014,781 B2 · Memory device supporting interleaved operations and memory system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,781 B2 - Document ID: US12014781B2 - Status: Granted - Kind: B2 - Application number: 17/507,326 - Filed: 2021-10-21 - Published: 2022-04-28 - Granted: 2024-06-18 - Earliest claimed: 2020-10-26 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Won Jae Choi; Jea Won Choi - Web page: https://patentgrep.com/patent/US12014781B2 ## CPC - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G11C 7/1042: {using interleaving techniques, i.e. read-write of one part of the memory while preparing another part} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system includes a first memory die including multiple planes each including a plurality of memory cells and a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die. After transferring an erase command to a plane among the multiple planes, the controller transfers a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane. ## Claims ### Claim 1 A memory system, comprising: a first memory die including multiple planes each including a plurality of memory cells; and a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die, wherein the controller is configured to, after transferring an erase command to a plane among the multiple planes, transfer a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane, and wherein the controller is configured to estimate an operation margin of the erase operation performed in the plane and adjust or change a sequence of the read command, the program command, and the check command to be transferred to the another plane. ### Claim 2 (depends on 1) The memory system of claim 1, further comprising: a second memory die, coupled to the controller via a second channel, the second memory die including multiple other planes, wherein the controller is configured to divide multiple commands performed in the first memory die and the second memory die into different groups corresponding to the first memory die and the second memory die. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the first memory die comprises: a voltage generator configured to generate voltages used in the multiple planes; a data buffer and distributor configured to distribute and transfer data input or output via the first channel over the multiple planes via data lines coupled to the multiple planes; and a control circuit configured to control the voltage generator and the data buffer and distributor and output a result of an operation performed in the multiple planes. ### Claim 4 (depends on 3) The memory system of claim 3, wherein the data buffer and distributor comprise multiple buffers, each buffer corresponding to each of the multiple planes. ### Claim 5 (depends on 3) The memory system of claim 3, wherein the control circuit is capable of changing or adjusting an execution sequence of commands input from the controller, to prevent another erase operation from being performed in other planes among the multiple planes while the first memory die performs the erase operation corresponding to the erase command in the plane. ### Claim 6 A memory system, comprising: a first memory die including multiple first planes each including a plurality of first memory cells; a second memory die including multiple second planes each including a plurality of second memory cells; and a controller configured to perform data communication with the first and second memory dies through first and second channels, wherein the controller is configured to transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to be performed in the first and second memory dies, and wherein the first memory die is configured to, while performing an erase operation in a plane of the multiple first planes based on commands input from the controller, perform a read operation, a program operation or a check operation in other planes of the multiple first planes based on the commands, and wherein the controller is configured to estimate an operation margin of the erase operation performed in the plane and adjust or change a sequence of the read command, the program command, and the check command to be transferred to the other planes. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the second memory die is configured to, while performing an erase operation in a plane of the multiple second planes based on other commands input from the controller, perform a read operation, a program operation, or a check operation in other planes of the multiple second planes based on the other commands. ### Claim 8 (depends on 6) The memory system of claim 6, wherein the first memory die comprises: a voltage generator configured to generate voltages used in the multiple first planes; a data buffer and distributor configured to distribute and transfer data input or output via the first channel over the multiple first planes via data lines coupled to the multiple first planes; and a control circuit configured to control the voltage generator and the data buffer and distributor and output a result of an operation performed in the multiple first planes. ### Claim 9 (depends on 8) The memory system of claim 8, wherein the data buffer and distributor comprise multiple buffers each corresponding to a plane of the multiple first planes. ### Claim 10 (depends on 8) The memory system of claim 8, wherein the control circuit is capable of changing or adjusting an execution sequence of the commands input from the controller, to prevent another erase operation from being performed in other planes among the multiple first planes while the first memory die performs the erase operation corresponding to the erase command in the plane among the multiple first planes. ### Claim 11 A memory device, comprising: a plurality of non-volatile memory cells divided into multiple groups; a control circuit configured to change or adjust an execution sequence of an erase operation, a program operation, a read operation, and a check operation performed on the plurality of non-volatile memory cells, and, while performing an erase operation in a group of the multiple groups, perform a read operation, a program operation, or a check operation in other groups of the multiple groups, and multiple data buffers and multiple command buffers, each data buffer and each command buffer corresponding to a group of the multiple groups, wherein the control circuit is configured to control input or output of the multiple data buffers and the multiple command buffers to change or adjust the execution sequence, and wherein the control circuit is configured to, when a command output from a command buffer among the multiple command buffers is an erase command, check whether an operation performed in the multiple groups is an erase operation to determine whether an operation corresponding to the command is executed. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the plurality of non-volatile memory cells and the control circuit are implemented in a single semiconductor chip. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the plurality of non-volatile memory cells and the control circuit are implemented in different semiconductor chips. ### Claim 14 (depends on 11) The memory device of claim 11, wherein the multiple data buffers and the multiple command buffers have a first-in, first-out (FIFO) data structure. ### Claim 15 (depends on 11) The memory device of claim 11, wherein the control circuit is configured to, when transmitting or receiving a data buffer among the multiple data buffers, obstruct data transmission/reception in other data buffers among the multiple data buffers. ### Claim 16 (depends on 11) The memory device of claim 11, wherein the control circuit is configured to change or adjust the execution sequence according to whether data transmission/reception is required for operations performed in the multiple groups.