# US 12,014,780 B2 · Memory circuit, memory device and operation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,780 B2 - Document ID: US12014780B2 - Status: Granted - Kind: B2 - Application number: 17/806,080 - Filed: 2022-06-09 - Published: 2022-12-15 - Granted: 2024-06-18 - Earliest claimed: 2021-06-10 - Assignees: National Central University - Applicants: National Central University - Inventors: E Ray Hsieh - Web page: https://patentgrep.com/patent/US12014780B2 ## CPC - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 11/223: {using MOS with ferroelectric gate insulating film} - G11C 11/2259: {Cell access} - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 11/2275: {Writing or programming circuits or methods} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/003: {Cell access} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 2213/53: Structure wherein the resistive material being in a transistor, e.g. gate - G11C 2213/79: Array wherein the access device being a transistor - G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure provides a memory device, which includes a plurality of electrically bipolar variable memory devices and a storage transistor. The electrically bipolar variable memory devices are electrically connected to a plurality of word lines respectively, the storage transistor is electrically connected to the electrically bipolar variable memory devices, where one end of each of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the electrically bipolar variable memory devices is electrically connected to the gate of the storage transistor. ## Claims ### Claim 1 A memory device, comprising: a plurality of electrically bipolar variable memory devices electrically connected to a plurality of word lines respectively; and a storage transistor electrically connected to the plurality of the electrically bipolar variable memory devices, wherein one end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the plurality of the word lines, and another end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a gate of the storage transistor, wherein the storage transistor comprises: the gate comprising one electrically conductive layer or a plurality of electrically conductive layers disposed above one dielectric layer or a plurality of dielectric layers disposed above a semiconductor substrate, the gate contacting one end of a gate contact plug, another end of the gate contact plug contacting a metal layer, and the plurality of the electrically bipolar variable memory devices formed on the metal layer; and a source/drain and another source/drain formed in the semiconductor substrate, and a channel region positioned between said source/drains under the gate rendering electrical signals. ### Claim 2 (depends on 1) The memory device of claim 1, wherein a source/drain of the storage transistor is electrically connected to a source line, and another source/drain of the storage transistor is electrically connected to a bit line. ### Claim 3 (depends on 1) The memory device of claim 1, further comprising: a control transistor connected the storage transistor in series, wherein a source/drain of the storage transistor is electrically connected to a source line, and another source/drain of the storage transistor is electrically connected to a source/drain of the control transistor, and another source/drain of the control transistor is electrically connected to a bit line. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the plurality of the electrically bipolar variable memory devices comprises: a first contact plug having a bottom being in contact with the metal layer; and one or a plurality of first electrically bipolar variable layers, wherein one side of each of said first electrically bipolar variable layers contacts one side of the first contact plug, each of the plurality of the word lines in parallel and separately contacts another side of each of said first electrically bipolar variable layers, each of said first electrically bipolar variable layers has first regions between said word lines and the first contact plug, and said first regions serves as the electrically bipolar variable memory devices. ### Claim 5 (depends on 4) The memory device of claim 4, wherein each of said first electrically bipolar variable layers is a bipolar variable resistance layer or a bipolar variable capacitance layer. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the source/drain contacts one end of a first source/drain contact plug, another end of the first source/drain contact plug contacts a source line, the another source/drain contacts one end of a second source/drain contact plug, and another end of the second source/drain contact plug is electrically connected to a bit line. ### Claim 7 A memory circuit, comprising: a plurality of memory devices arranged in an array, each of the memory devices comprising: a plurality of electrically bipolar variable memory devices electrically connected to a plurality of word lines respectively; and a storage transistor electrically connected to the plurality of the electrically bipolar variable memory devices, wherein one end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a gate of the storage transistor, wherein the storage transistor comprises: the gate comprising one electrically conductive layer or a plurality of electrically conductive layers disposed above one dielectric layer or a plurality of dielectric layers disposed above a semiconductor substrate, the gate contacting one end of a gate contact plug, another end of the gate contact plug contacting a metal layer, and the plurality of the electrically bipolar variable memory devices formed on the metal layer; and a source/drain and another source/drain formed in the semiconductor substrate, and a channel region positioned between said source/drains under the gate rendering electrical signals. ### Claim 8 (depends on 7) The memory circuit of claim 7, wherein a source/drain of the storage transistor is electrically connected to one of a plurality of source lines, and another source/drain of the storage transistor is electrically connected to one of a plurality of bit lines, the plurality of source lines are electrically connected to a source line decoder with a control circuit, the plurality of bit lines are electrically connected to a bit line decoder with a control circuit and a sense circuit, and the plurality of the word lines are electrically connected to a word line decoder with a control circuit. ### Claim 9 (depends on 7) The memory circuit of claim 7, wherein the each of the memory devices comprises: a control transistor connected the storage transistor in series, wherein a source/drain of the storage transistor is electrically connected to one of a plurality of source lines, another source/drain of the storage transistor is electrically connected to a source/drain of the control transistor, another source/drain of the control transistor is electrically connected to one of a plurality of bit lines, a gate of the control transistor is electrically connected to one of a plurality of control lines, the plurality of source lines are electrically connected to a source line decoder with a control circuit, the plurality of bit lines are electrically connected to a bit line decoder with a control circuit, the plurality of word lines are electrically connected to a word line decoder with a control circuit, and the plurality of control lines are electrically connected to a control line decoder with a control circuit. ### Claim 10 An operation method of a memory device, the memory device comprising a storage transistor and a plurality of electrically bipolar variable memory devices, the plurality of electrically bipolar variable memory devices electrically connected to a plurality of word lines respectively, and the operation method comprising steps of: when programming one of the plurality of electrically bipolar variable memory devices, applying a programming voltage to a corresponding word line of the plurality of word lines, applying a zero voltage to a bit line, and floating a source line, wherein one end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the plurality of the word lines, another end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a gate of the storage transistor, a source/drain of the storage transistor is electrically connected to the source line, and another source/drain of the storage transistor is electrically connected to the bit line. ### Claim 11 (depends on 10) The operation method of claim 10, further comprising: when erasing the one of the plurality of electrically bipolar variable memory devices, applying the zero voltage to the corresponding word line, applying an erasing voltage to the bit line, and floating the source line. ### Claim 12 (depends on 10) The operation method of claim 10, further comprising: when reading the one of the plurality of electrically bipolar variable memory devices, applying a read voltage to the corresponding word line, applying 0.1 times to 1 time of an operation voltage to the bit line, and applying the zero voltage to the source line. ### Claim 13 (depends on 10) The operation method of claim 10, further comprising: when the one of the plurality of electrically bipolar variable memory devices is not selected, floating the corresponding word line, and applying the zero voltage to the bit line and the source line. ### Claim 14 (depends on 10) The operation method of claim 10, further comprising: when refreshing the one of the plurality of electrically bipolar variable memory devices, periodically programming the one of the plurality of electrically bipolar variable memory devices every predetermined time. ### Claim 15 (depends on 10) The operation method of claim 10, wherein the memory device further comprises a control transistor connected the storage transistor in series, a source/drain of the storage transistor is electrically connected to the source line, and another source/drain of the storage transistor is electrically connected to a source/drain of the control transistor, and another source/drain of the control transistor is electrically connected to the bit line, a gate of the control transistor is electrically connected to a control line, the step of programming one of the plurality of electrically bipolar variable memory devices comprises: applying a voltage greater than or equivalent to an operation voltage to the control line to turn on the control transistor, so that the another source/drain of the storage transistor is electrically connected to the bit line through the control transistor. ### Claim 16 (depends on 15) The operation method of claim 15, further comprising: when erasing the one of the plurality of electrically bipolar variable memory devices, applying the voltage greater than or equivalent to the operation voltage to the control line, applying the zero voltage to the corresponding word line, applying an erasing voltage to the bit line, and floating the source line. ### Claim 17 (depends on 15) The operation method of claim 15, further comprising: when reading the one of the plurality of electrically bipolar variable memory devices, applying the operation voltage to the control line, applying a read voltage to the corresponding word line, applying 0.1 times to 1 time of the operation voltage to the bit line, and applying the zero voltage to the source line. ### Claim 18 (depends on 15) The operation method of claim 15, further comprising: when the one of the plurality of electrically bipolar variable memory devices is not selected, floating the corresponding word line, and applying the zero voltage to the control line, the bit line and the source line. ### Claim 19 (depends on 15) The operation method of claim 15, further comprising: when refreshing the one of the plurality of electrically bipolar variable memory devices, periodically programming the one of the plurality of electrically bipolar variable memory devices every predetermined time.