# US 12,014,779 B2 · Programming techniques for polarity-based memory cells

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- Number: US 12,014,779 B2
- Document ID: US12014779B2
- Status: Granted
- Kind: B2
- Application number: 17/885,131
- Filed: 2022-08-10
- Published: 2023-02-02
- Granted: 2024-06-18
- Earliest claimed: 2020-08-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Innocenzo Tortorelli; Mattia Boniardi; Mattia Robustelli
- Web page: https://patentgrep.com/patent/US12014779B2

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/10: Programming or data input circuits
- G11C 7/1009: {Data masking during input/output}
- G11C 13/003: {Cell access}
- G11C 13/0061: {Timing circuits or methods}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/5607: {using magnetic storage elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2013/0073: {Write using bi-directional cell biasing}
- G11C 2013/0088: {Write with the simultaneous writing of a plurality of cells}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.

## Claims

### Claim 1

A method, comprising:
receiving a write command indicating data to be written to a plurality of memory cells of a memory device;
applying a first pulse to a first set of memory cells of the plurality of memory cells based at least in part on the data comprising a first data type; and
applying a second pulse to a second set of memory cells of the plurality of memory cells based at least in part on the data comprising a combination of the first data type and a second data type.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
applying a third pulse to a third set of memory cells of the plurality of memory cells before applying the first pulse to the first set of memory cells,
wherein the third set of memory cells is different than the first set of memory cells or the second set of memory cells, or wherein the third set of memory cells comprises a subset of the first set of memory cells or the second set of memory cells.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
detecting, based at least in part on applying the third pulse, an absence of an indication that one or more memory cells of the third set of memory cells store the second data type; and
refraining from applying the first pulse based at least in part on the absence of the indication.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
determining, after applying the first pulse to the first set of memory cells, that the one or more memory cells of the third set of memory cells store the second data type; and
applying the second pulse based at least in part on the determining.

### Claim 5 (depends on 4)

The method of claim 4, wherein the absence of the indication is based at least in part on a magnitude of the third pulse satisfying a respective threshold for each of the one or more memory cells of the third set of memory cells.

### Claim 6 (depends on 2)

The method of claim 2, further comprising:
detecting, based at least in part on applying the third pulse, an indication that the first set of memory cells store the second data type,
wherein applying the first pulse to the first set of memory cells is based at least in part on the indication.

### Claim 7 (depends on 1)

The method of claim 1, wherein applying the second pulse to the second set of memory cells comprises:
applying the second pulse to the second set of memory cells irrespective of whether the second set of memory cells store the second data type.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
identifying a target memory cell based at least in part on the write command indicating the target memory cell, wherein the target memory cell is associated with the second set of memory cells;
refraining, based at least in part on the write command indicating the target memory cell, from detecting an indication that the target memory cell stores the second data type; and
refraining, based at least in part on the write command indicating the target memory cell, from detecting an absence of the indication that the target memory cell stores the second data type.

### Claim 9

An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive a write command indicating data to be written to a plurality of memory cells of the memory device;
apply a first pulse to a first set of memory cells of the plurality of memory cells based at least in part on the data comprising a first data type; and
apply a second pulse to a second set of memory cells of the plurality of memory cells based at least in part on the data comprising a combination of the first data type and a second data type.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the controller is further configured to cause the apparatus to:
apply a third pulse to a third set of memory cells of the plurality of memory cells before applying the first pulse to the first set of memory cells,
wherein the third set of memory cells is different than the first set of memory cells or the second set of memory cells, or wherein the third set of memory cells comprises a subset of the first set of memory cells or the second set of memory cells.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to:
detect, based at least in part on applying the third pulse, an absence of an indication that one or more memory cells of the third set of memory cells store the second data type; and
refrain from applying the first pulse based at least in part on the absence of the indication.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the controller is further configured to cause the apparatus to:
determine, after applying the first pulse to the first set of memory cells, that the one or more memory cells of the third set of memory cells store the second data type; and
apply the second pulse based at least in part on the determination.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the absence of the indication is based at least in part on a magnitude of the third pulse satisfying a respective threshold for each of the one or more memory cells of the third set of memory cells.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the controller is configured to cause the apparatus to:
detect, based at least in part on applying the third pulse, an indication that the first set of memory cells store the second data type,
wherein to apply the first pulse to the first set of memory cells is based at least in part on the indication.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein the controller is configured to cause the apparatus to:
apply the second pulse to the second set of memory cells irrespective of whether the second set of memory cells store the second data type.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the controller is further configured to cause the apparatus to:
identify a target memory cell based at least in part on the write command indicating the target memory cell, wherein the target memory cell is associated with the second set of memory cells;
refrain, based at least in part on the write command indicating the target memory cell, from detecting an indication that the target memory cell stores the second data type; and
refrain, based at least in part on the write command indicating the target memory cell, from detecting an absence of the indication that the target memory cell stores the second data type.

### Claim 17

A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
receive a write command indicating data to be written to a plurality of memory cells of a memory device;
apply a first pulse to a first set of memory cells of the plurality of memory cells based at least in part on the data comprising a first data type; and
apply a second pulse to a second set of memory cells of the plurality of memory cells based at least in part on the data comprising a combination of the first data type and a second data type.

### Claim 18 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to:
apply a third pulse to a third set of memory cells of the plurality of memory cells before applying the first pulse to the first set of memory cells,
wherein the third set of memory cells is different than the first set of memory cells or the second set of memory cells, or wherein the third set of memory cells comprises a subset of the first set of memory cells or the second set of memory cells.

### Claim 19 (depends on 18)

The non-transitory computer-readable medium of claim 18, wherein the instructions are further executable by the processor to:
detect, based at least in part on applying the third pulse, an absence of an indication that one or more memory cells of the third set of memory cells store the second data type; and
refrain from applying the first pulse based at least in part on the absence of the indication.

### Claim 20 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the instructions are further executable by the processor to:
determine, after applying the first pulse to the first set of memory cells, that the one or more memory cells of the third set of memory cells store the second data type; and
apply the second pulse based at least in part on the determination.