# US 12,014,778 B2 · In-line programming adjustment of a memory cell in a memory sub-system

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- Number: US 12,014,778 B2
- Document ID: US12014778B2
- Status: Granted
- Kind: B2
- Application number: 17/670,037
- Filed: 2022-02-11
- Published: 2022-09-29
- Granted: 2024-06-18
- Earliest claimed: 2021-03-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sheyang Ning; Lawrence Celso Miranda; Zhengyi Zhang; Tomoko Ogura Iwasaki
- Web page: https://patentgrep.com/patent/US12014778B2

## CPC

- G11C 16/10: Programming or data input circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.

## Claims

### Claim 1

A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell of the plurality of memory cells to be programmed to a first target voltage level representing a first programming level;
performing a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level;
causing first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level;
causing the cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level; and
causing, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell at a reduced programming stress level.

### Claim 2 (depends on 1)

The memory device of claim 1, the operations further comprising causing, in view of the first data, an inhibit voltage to be applied to a bitline corresponding to the memory cell during an application of a second programming pulse to the wordline associated with the memory cell.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the cache is refreshed and the further programming pulse is caused to be applied prior to completion of the programming algorithm.

### Claim 4 (depends on 1)

The memory device of claim 1, the operations further comprising maintaining an additional cache storing the second data detected by one or more sense amplifiers associated with the memory array.

### Claim 5 (depends on 4)

The memory device of claim 4, the operations further comprising writing the second data from the additional cache to the cache to cause the cache to be refreshed.

### Claim 6 (depends on 1)

The memory device of claim 1, the operations further comprising detecting a decrease of the threshold voltage of the memory cells from a first condition where the threshold voltage exceeds the first target voltage level to a second condition where the threshold voltage is less than the program, wherein the cache is refreshed in response to the detecting.

### Claim 7 (depends on 1)

The memory device of claim 1, the operations further comprising:
causing one or more additional programming pulses to be applied to the wordline associated with the memory cell;
causing the cache to be refreshed to store additional data; and
terminating application of the one or more additional programming pulses in response to a determination that the additional data indicates that the threshold voltage of the memory cell exceeds the first target voltage level.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the reduced programming stress level is caused by one of:
applying a bitline voltage level that is lower than an inhibit voltage level to a bitline associated with the memory cell;
boosting a pillar voltage associated with the memory cell; or
reducing, during application of the further programming pulse, a voltage level applied to the bitline associated with the memory cell from the inhibit voltage level to a reduced voltage level.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the reduced programming stress level is caused by executing a level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is lower than the first programming level prior to causing the further programming pulse to be applied to the wordline associated with the memory cell.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the programming algorithm comprises one of an incremental step pulse programming (ISPP) algorithm or an all-levels programming algorithm.

### Claim 11

A method comprising:
initiating a programming algorithm to program a memory cell to a first target voltage level representing a first programming level of a plurality of programming levels;
causing a first programming pulse of the programming algorithm to be applied to a wordline associated with the memory cell;
performing a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level;
causing first data to be stored in a first cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level;
causing the first cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level; and
causing, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell at a reduced programming stress.

### Claim 12 (depends on 11)

The method of claim 11, further comprising causing, in view of the first data stored in the first cache, an inhibit voltage to be applied to a bitline corresponding to the memory cell during an application of a second programming pulse to the wordline associated with the memory cell.

### Claim 13 (depends on 11)

The method of claim 11, wherein the further programming pulse is caused to be applied prior to completion of the programming algorithm.

### Claim 14 (depends on 11)

The method of claim 11, further comprising maintaining a second cache storing the second data detected by a sense amplifier configured to sense the threshold voltage of the memory cell.

### Claim 15 (depends on 14)

The method of claim 14, further comprising writing the second data from the second cache to the first cache to cause the first cache to be refreshed.

### Claim 16 (depends on 11)

The method of claim 11, further comprising executing a level shifting operation comprises logically shifting a designation associated with the memory cell to a second programming level that is lower than the first programming level prior to causing the further programming pulse to be applied to the wordline associated with the memory cell.

### Claim 17 (depends on 11)

The method of claim 11, wherein the first cache is refreshed and the further programming pulse is caused to be applied prior to completion of the programming algorithm.

### Claim 18 (depends on 11)

The method of claim 11, further comprising detecting a decrease of the threshold voltage of the memory cell from a first condition where the threshold voltage exceeds the first target voltage level to a second condition where the threshold voltage is less than the program, wherein the first cache is refreshed in response to the detecting.

### Claim 19

A memory device comprising:
a memory array comprising a plurality of memory cells comprising a first memory cell; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a programming algorithm to program a memory cell to a first programming level of a plurality of programming levels;
causing, at a first time, a first programming pulse of the programming algorithm to be applied to a wordline associated with the memory cell;
performing a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds a first target voltage level;
causing first data to be stored in a first cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level;
causing the first cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level; and
causing, at a second time, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell at a reduced programming stress level.

### Claim 20 (depends on 19)

The memory device of claim 19, the operations further comprising detecting a decrease of the threshold voltage of the memory cells from a first condition where the threshold voltage exceeds the first target voltage level to a second condition where the threshold voltage is less than the program, wherein the first cache is refreshed in response to the detecting.