# US 12,014,775 B2 · Write error counter for media management in a memory device

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- Number: US 12,014,775 B2
- Document ID: US12014775B2
- Status: Granted
- Kind: B2
- Application number: 17/732,353
- Filed: 2022-04-28
- Published: 2023-11-02
- Granted: 2024-06-18
- Earliest claimed: 2022-04-28
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John Christopher M. Sancon
- Web page: https://patentgrep.com/patent/US12014775B2

## CPC

- G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes a sense amplifier, a counter, and memory having memory cells. Access lines are used to select the memory cells for performing write operations. The memory device includes a controller to control the applying of a voltage to the memory cell. The voltage is applied during a write operation using the access lines. The sense amplifier is used to determine whether the memory cell reaches a threshold state or snaps. In response to determining that the memory cell does not snap, a write error count is incremented using the counter. The controller reads the counter to determine the write error count, and based on the write error count, the controller performs one or more media management or memory device control actions.

## Claims

### Claim 1

An apparatus comprising:
a counter;
a memory array having a plurality of memory cells; and
at least one controller configured to:
determine whether a memory cell snaps due to applying at least one pulse to the memory cell;
in response to determining that the memory cell does not snap, increment a count using the counter;
determine whether the count has reached a threshold; and
in response to determining that the count has reached the threshold, perform an action associated with the memory array.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein:
applying the at least one pulse comprises applying, during a write operation, a first pulse to the memory cell, and after applying the first pulse, applying a second pulse to the memory cell; and
the action associated with the memory array is applying a third pulse to the memory cell as part of the write operation, and the third pulse has a greater voltage magnitude than a voltage magnitude of either the first or second pulses.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a sense amplifier, wherein determining whether the memory cell snaps comprises sensing, using the sense amplifier, a current or voltage associated with the memory cell.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein determining whether the memory cell snaps comprises determining whether a current associated with the memory cell exceeds a threshold.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the pulse is a first pulse and the controller is further configured to:
determine whether the memory cell snaps due to applying the first pulse; and
in response to determining that the memory cell does not snap due to applying the first pulse, increase a voltage of a second pulse applied to the memory cell.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the memory array is a planar two-dimensional array, and the memory cell is located at a crossing of a wordline and a bitline.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising logic circuitry to generate write error signals, wherein the write error signals cause the counter to increment the count of write errors.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the counter is a multi-bit counter that encodes the write error signals to provide an encoded write error count.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the write error signals are inputs to a logical OR gate that generates an error output, and the error output is an input to the counter.

### Claim 10 (depends on 1)

The apparatus of claim 1, further comprising a register, wherein the count of write errors is stored in the register, and wherein the controller is further configured to read the register to determine whether the count has reached the threshold.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the counter accumulates the count of write errors over multiple write operations, and the controller is further configured to read the count after a defined number of write operations have been performed.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the at least one controller comprises a first controller on a first die that includes the memory array, and a second controller on a second die.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein:
the controller is further configured to determine whether an electrical distance of the memory cell satisfies a condition; and
the count of write errors is incremented further in response to determining that the electrical distance satisfies the condition.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein determining whether the electrical distance satisfies the condition comprises determining whether an address of the memory cell is greater than a threshold value or within a defined address range.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the electrical distance is an electrical distance from a wordline or bitline driver that applies the pulse.

### Claim 16 (depends on 1)

The apparatus of claim 1, wherein applying the at least one pulse comprises:
applying, during a write operation, a first pulse to the memory cell; and
after applying the first pulse, applying a second pulse to the memory cell.

### Claim 17 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to perform write verifications during write operations for the memory cells.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein the memory cell is a phase change memory cell, and the first pulse is used for drift cancellation.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein:
the first pulse has a first polarity;
the second pulse has a second polarity; and
the second polarity is opposite to the first polarity.

### Claim 20 (depends on 16)

The apparatus of claim 16, wherein a voltage magnitude of the second pulse is greater than a voltage magnitude of the first pulse.

### Claim 21 (depends on 16)

The apparatus of claim 16, wherein the first and second pulses are applied using a wordline and a bitline of the memory array.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein the memory array is a vertical three-dimensional array, and the bitline is a vertical pillar crossing a horizontal plane in which the wordline is located.

### Claim 23

An apparatus comprising:
a sense amplifier;
a counter;
memory comprising a plurality of memory cells;
access lines; and
control circuitry configured to:
apply, using at least one of the access lines, a voltage to a memory cell;
determine, using the sense amplifier, whether the memory cell reaches a threshold state after applying the voltage;
in response to determining that the memory cell does not reach the threshold state, increment a count using the counter;
read the counter to determine the count; and
based on the determined count, perform at least one action.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the action includes at least one of:
refreshing the memory cell;
retrying a write operation;
wear leveling;
retirement of a block or other portion of the memory;
write cycle binning in which a selection voltage is increased for at least one bin;
changing a shape for a waveform of a write voltage applied to the memory cells; or
increasing a voltage applied to at least one of a wordline or a bitline used to select the memory cells.

### Claim 25 (depends on 23)

The apparatus of claim 23, further comprising a register, wherein:
the count is stored in the register;
reading the counter comprises reading the register; and
the action is performed based on whether the count has reached a threshold.

### Claim 26 (depends on 23)

The apparatus of claim 23, wherein determining whether the memory cell reaches the threshold state is only performed if an electrical distance of the memory cell satisfies a condition.

### Claim 27 (depends on 26)

The apparatus of claim 26, wherein the condition includes an address of the memory cell being within an address range.

### Claim 28

A method comprising:
determining whether each of a plurality of memory cells reaches a respective threshold state after applying a voltage;
in response to determining that at least one of the memory cells does not reach the respective threshold state, incrementing a counter;
reading the counter; and
based on reading the counter, performing at least one action.

### Claim 29 (depends on 28)

The method of claim 28, wherein reading the counter comprises determining a number of errors that occur over multiple write operations.

### Claim 30 (depends on 28)

The method of claim 28, wherein the action includes increasing a voltage applied to at least one of a wordline or bitline used to select memory cells during write operations.

### Claim 31 (depends on 28)

The method of claim 28, wherein the plurality of memory cells is accessed using a common address.