# US 12,014,774 B2 · Memory selector threshold voltage recovery

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- Number: US 12,014,774 B2
- Document ID: US12014774B2
- Status: Granted
- Kind: B2
- Application number: 17/658,701
- Filed: 2022-04-11
- Published: 2023-08-10
- Granted: 2024-06-18
- Earliest claimed: 2022-02-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Elia Ambrosi; Cheng-Hsien Wu; Hengyuan Lee; Xinyu Bao
- Web page: https://patentgrep.com/patent/US12014774B2

## CPC

- G11C 13/003: {Cell access}
- G11C 11/1659: {Cell access}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/06: Acceleration testing
- H10B 63/10: Phase change RAM [PCRAM, PRAM] devices
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C 2029/0409: {Online test}
- G11C 2213/15: Current-voltage curve
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method includes applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector into an on-state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse the selector has a first voltage threshold, wherein after applying the second voltage pulse the selector has a second voltage threshold that is less than the first voltage threshold; and after applying the second voltage pulse, applying a third voltage pulse across the memory cell, wherein the third voltage pulse switches the selector into an on-state; wherein the selector remains continuously in an off-state between the first voltage pulse and the third voltage pulse.

## Claims

### Claim 1

A method comprising:
applying a first voltage pulse across a memory cell, wherein the memory cell comprises a selector, wherein the first voltage pulse switches the selector into an on-state;
after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse the selector has a first voltage threshold, wherein after applying the second voltage pulse the selector has a second voltage threshold that is less than the first voltage threshold, wherein the second voltage pulse has a magnitude that is less than a magnitude of the first voltage threshold and less than a magnitude of the second voltage threshold; and
after applying the second voltage pulse, applying a third voltage pulse across the memory cell, wherein the third voltage pulse switches the selector into an on-state; wherein the selector remains continuously in an off-state between the first voltage pulse and the third voltage pulse.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first voltage pulse and the third voltage pulse have a first voltage polarity, and wherein the second voltage pulse has a second voltage polarity that is opposite from the first voltage polarity.

### Claim 3 (depends on 1)

The method of claim 1 further comprising, after applying the first voltage pulse and before applying the second voltage pulse, applying a fourth voltage pulse.

### Claim 4 (depends on 1)

The method of claim 1, wherein the selector comprises a layer of GeCTe.

### Claim 5 (depends on 1)

The method of claim 1, wherein a duration of time between the first voltage pulse and the second voltage pulse is greater than one second.

### Claim 6 (depends on 1)

The method of claim 1, wherein the third voltage pulse is applied immediately after the second voltage pulse is applied.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first voltage threshold is greater than the second voltage threshold by a voltage difference in the range of 50 mV to 500 mV.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second voltage pulse is applied continuously from the first voltage pulse to the third voltage pulse.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first voltage pulse is part of a reading operation performed on the memory cell.

### Claim 10

A method comprising:
performing a subthreshold stress process on a memory array, wherein each memory cell of the memory array comprises a chalcogenide selector, wherein performing the subthreshold stress process comprises:
applying a first voltage between a first word line and a first bit line of the memory array, wherein a first memory cell of the memory array is connected to the first word line and the first bit line, wherein at the start of the subthreshold stress process the chalcogenide selector of the first memory cell has a first threshold voltage, wherein a magnitude of the first voltage is less than the first threshold voltage, wherein at the end of the subthreshold stress process the chalcogenide selector of the first memory cell has a second threshold voltage that is smaller than the first threshold voltage; and
before performing the subthreshold stress process, applying a second voltage between the first word line and the first bit line of the memory array, wherein the second voltage is greater than the first threshold voltage, wherein a polarity of the second voltage is opposite that of the first voltage, wherein no voltage is applied between the first word line and the first bit line in the time between the applying of the second voltage and the applying of the first voltage.

### Claim 11 (depends on 10)

The method of claim 10, wherein performing the subthreshold stress process further comprises simultaneously applying the first voltage between the first word line and a second bit line of the memory array, wherein a second memory cell of the memory array is connected to the first word line and the second bit line.

### Claim 12 (depends on 10)

The method of claim 10, wherein applying the first voltage comprises applying a series of pulses of the first voltage.

### Claim 13 (depends on 10)

The method of claim 10 further comprising determining an elapsed time since the applying of the second voltage, wherein the applying of the first voltage is based on the elapsed time.

### Claim 14 (depends on 10)

The method of claim 10, wherein the memory array is a Phase-Change Random Access Memory (PCRAM) array.

### Claim 15

A method comprising:
determining a target threshold voltage for a chalcogenide selector, wherein the chalcogenide selector has a threshold voltage that is different than the target threshold voltage;
applying a first voltage pulse to the chalcogenide selector, wherein a magnitude of the first voltage pulse is less than the target threshold voltage;
after applying the first voltage pulse, applying a test voltage pulse to the chalcogenide selector, wherein the magnitude of the test voltage pulse is at least the magnitude of the target threshold voltage;
determining whether the test voltage pulse successfully switched the chalcogenide selector into an on-state; and
based on the determining of the switching of the chalcogenide selector into an on-state, applying a second voltage pulse to the chalcogenide selector, wherein a duration of the second voltage pulse is longer than a duration of the first voltage pulse and/or a magnitude of the second voltage pulse is larger than a magnitude of the first voltage pulse.

### Claim 16 (depends on 15)

The method of claim 15 further comprising, based on the determining of the switching of the chalcogenide selector into an on-state, applying a third voltage pulse to the chalcogenide selector before applying the second voltage pulse.

### Claim 17 (depends on 15)

The method of claim 15, wherein the magnitude of the second voltage pulse is less than the target threshold voltage.

### Claim 18 (depends on 15)

The method of claim 15, wherein the chalcogenide selector is the selector of a memory cell of a PCRAM memory array.

### Claim 19 (depends on 15)

The method of claim 15, wherein the second voltage pulse is not applied after determining that the chalcogenide selector was successfully switched into an on-state.

### Claim 20 (depends on 15)

The method of claim 15, wherein the second voltage pulse has a polarity opposite to that of the test voltage pulse.