# US 12,014,773 B2 · Semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,773 B2 - Document ID: US12014773B2 - Status: Granted - Kind: B2 - Application number: 17/882,128 - Filed: 2022-08-05 - Published: 2022-11-24 - Granted: 2024-06-18 - Earliest claimed: 2020-07-15 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hiroki Date; Takeshi Nakano - Web page: https://patentgrep.com/patent/US12014773B2 ## CPC - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/32: Timing circuits - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C 2211/5643: Multilevel memory comprising cache storage devices - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line. ## Claims ### Claim 1 A semiconductor storage device comprising: a first memory cell; a second memory cell adjacent to the first memory cell and connected to the first memory cell in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit configured to: in a first read operation reading data stored in the first memory cell, apply a first voltage to the first word line and a second voltage to the second word line at first timing, apply a first read voltage lower than the first voltage, to the first word line at second timing after the first timing, and apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line at third timing after the second timing. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, wherein the control circuit is configured to: in a second read operation reading data stored in the first memory cell and different from the first read operation, apply the first voltage to the first word line, and a fourth voltage lower than the second voltage and higher than the third voltage to the second word line at fourth timing, apply a second read voltage lower than the first voltage and higher than the first read voltage, to the first word line at fifth timing after the fourth timing, and apply the third voltage to the second word line at sixth timing after fifth timing. ### Claim 3 (depends on 2) The semiconductor storage device according to claim 2, wherein a first period being from the second timing to the third timing, a second period being from the fifth timing to the sixth timing, and the first period and the second period are different. ### Claim 4 (depends on 3) The semiconductor storage device according to claim 3, wherein the first period is longer than the second period. ### Claim 5 (depends on 1) The semiconductor storage device according to claim 1, wherein a voltage difference between the second voltage and the third voltage is correlated to a voltage difference between the third voltage and the first read voltage. ### Claim 6 (depends on 1) The semiconductor storage device according to claim 1, wherein a first period is correlated to a voltage difference between the third voltage and the first read voltage, the first period being from the second timing to the third timing. ### Claim 7 (depends on 2) The semiconductor storage device according to claim 2, wherein the control circuit is configured to assert a first strobe signal for the first read operation, during the application of the first read voltage to the first word line, and the control circuit is configured to assert a second strobe signal for the second read operation, during the application of the second read voltage to the first word line. ### Claim 8 (depends on 1) The semiconductor storage device according to claim 1, further comprising: a third memory cell adjacent to the second memory cell and connected to the first memory cell in series via the second memory cell; and a third word line connected to the third memory cell, wherein the control circuit is configured to apply the first voltage to the third word line in the first read operation. ### Claim 9 (depends on 1) The semiconductor storage device according to claim 1, wherein the control circuit is configured to, in the first read operation, apply a third read voltage, lower than the first read voltage, to the first word line at seventh timing after the second timing, and apply a fifth voltage higher than the third voltage and different from the second voltage, to the second word line at eighth timing after third timing, and apply the third voltage to the second word line at ninth timing after the eighth timing. ### Claim 10 (depends on 9) The semiconductor storage device according to claim 9, wherein the seventh timing is same as the eighth timing. ### Claim 11 (depends on 9) The semiconductor storage device according to claim 9, wherein a first period being from the second timing to the third timing, a third period being from the seventh timing to the ninth timing, and the first period and the third period being different. ### Claim 12 (depends on 9) The semiconductor storage device according to claim 9, wherein a voltage difference between the fifth voltage and the third voltage is correlated to a voltage difference between the first read voltage and the third read voltage. ### Claim 13 (depends on 9) The semiconductor storage device according to claim 9, wherein a third period is correlated to a voltage difference between the first read voltage and the third read voltage, the third period being from the seventh timing to the ninth timing. ### Claim 14 (depends on 9) The semiconductor storage device according to claim 9, wherein the control circuit is configured to assert a first strobe signal for the first read operation during the application of the first read voltage to the first word line, and assert a second strobe signal for the first read operation during the application of the third read voltage to the first word line. ### Claim 15 (depends on 1) The semiconductor storage device according to claim 1, wherein the control circuit is configured to, in the first read operation, apply a third read voltage lower than the first read voltage to the first word line at seventh timing after the second timing, and apply a sixth voltage lower than the third voltage and higher than the first voltage, to the second word line at eight timing after the third timing. ### Claim 16 (depends on 15) The semiconductor storage device according to claim 15, wherein a first period being from the second timing to the third timing a fourth period being from the seventh timing to the eighth timing, and the first period and the fourth period being different. ### Claim 17 (depends on 15) The semiconductor storage device according to claim 15, wherein a voltage difference between the third voltage and the sixth voltage is correlated to a voltage difference between the first read voltage and the third read voltage. ### Claim 18 (depends on 15) The semiconductor storage device according to claim 15, wherein a fourth period is correlate to a voltage difference between the first read voltage and the third read voltage, the fourth period being from the seventh timing to the eighth timing. ### Claim 19 (depends on 15) The semiconductor storage device according to claim 15, wherein the control circuit is configured to assert a first strobe signal for the first read operation, during the application of the first read voltage to the first word line, and assert a second strobe signal for the first read operation, during the application of the third read voltage to the first word line. ### Claim 20 (depends on 1) A semiconductor storage device comprising: the semiconductor storage device according to claim 1; and a memory controller configured to control the semiconductor storage device.