# US 12,014,772 B2 · Storage controller and storage device including the same

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- Number: US 12,014,772 B2
- Document ID: US12014772B2
- Status: Granted
- Kind: B2
- Application number: 17/847,948
- Filed: 2022-06-23
- Published: 2023-05-18
- Granted: 2024-06-18
- Earliest claimed: 2021-11-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong Eun Shin; Jeong Uk Kang; Hyun Jin Choi
- Web page: https://patentgrep.com/patent/US12014772B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times, where N is a positive integer greater than 1, includes a write amplification manager and a central processing unit. The write amplification manager checks whether the first data is invalid data before an Nth programming of the first memory cell is performed, and the central processing unit does not perform the N-th programming of the first memory cell when the first data is the invalid data.

## Claims

### Claim 1

A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times (N being a positive integer greater than 1), the storage controller comprising:
a write amplification (WAF) manager configured to check whether the first data is invalid data before an Nth programming of the first memory cell is performed; and
a central processing unit (CPU) configured not to perform the N-th programming of the first memory cell when the first data is the invalid data.

### Claim 2 (depends on 1)

The storage controller of claim 1, further comprising a buffer memory configured to store the first data,
wherein the WAF manager comprises a buffer memory checker configured to communicate with the buffer memory and check whether the first data stored in the buffer memory is the invalid data.

### Claim 3 (depends on 1)

The storage controller of claim 1, further comprising a flash translation layer (FTL) configured to perform address mapping by using a mapping table which stores mapping information between a first logical address of the first data and a first physical address of the first data,
wherein the WAF manager comprises an FTL checker configured to communicate with the FTL and check whether the first data in the mapping table is the invalid data.

### Claim 4 (depends on 1)

The storage controller of claim 1, wherein, when the first data is trimmed data, the first data is the invalid data.

### Claim 5 (depends on 1)

The storage controller of claim 1, wherein, when the first data is not mapped in a mapping table, the first data is the invalid data.

### Claim 6 (depends on 1)

The storage controller of claim 1, wherein second data is written to a second memory cell connected to a same word line as the first memory cell by performing programming of the second memory cell N-times, and
wherein, when the first data is the invalid data, the Nth programming of the first memory cell is not performed and the Nth programming of the second memory cell is performed to write the second data.

### Claim 7 (depends on 6)

The storage controller of claim 6, wherein the storage controller performs programming of a third memory cell N-times, the third memory cell being connected to the same word line as the first memory cell and the second memory cell.

### Claim 8

A storage device for writing first data to a first memory cell by performing programming of the first memory cell N-times (N being a positive integer greater than 1), the storage device comprising:
a non-volatile memory (NVM) device comprising the first memory cell; and
a storage controller configured to write the first data to the first memory cell,
wherein the storage controller comprises:
a write amplification (WAF) manager configured to check whether the first data is invalid data before an Nth programming of the first memory cell is performed; and
a central processing unit (CPU) configured not to perform the N-th programming of the first memory cell when the first data is the invalid data.

### Claim 9 (depends on 8)

The storage device of claim 8, wherein the storage controller further comprises a buffer memory configured to store the first data, and
wherein the WAF manager comprises a buffer memory checker configured to communication with the buffer memory and check whether the first data stored in the buffer memory is the invalid data.

### Claim 10 (depends on 8)

The storage device of claim 8, wherein the storage controller further comprises a flash translation layer (FTL) configured to perform address mapping by using a mapping table which stores mapping information between a first logical address of the first data and a first physical address of the first data, and
wherein the WAF manager comprises an FTL checker configured to communicate with the FTL and check whether the first data in the mapping table is the invalid data.

### Claim 11 (depends on 8)

The storage device of claim 8, wherein, when the first data is trimmed data, the first data is the invalid data.

### Claim 12 (depends on 8)

The storage device of claim 8, wherein, when the first data is not mapped in a mapping table, the first data is the invalid data.

### Claim 13 (depends on 8)

The storage device of claim 8, wherein second data is written to a second memory cell connected to a same word line as the first memory cell by performing programming of the second memory cell N-times, and
wherein, when the first data is the invalid data, the Nth programming of the first memory cell is not performed and the Nth programming of the second memory cell is performed to write the second data.

### Claim 14 (depends on 13)

The storage device of claim 13, wherein the storage controller performs programming of a third memory cell N-times, the third memory cell being connected to the same word line as the first memory cell and the second memory cell.

### Claim 15

A storage device for writing first data to a first memory block and writing second data to a second memory block by performing programming of each of the first memory block and the second memory block N-times (N being a positive integer greater than 1), the storage device comprising:
a non-volatile memory (NVM) device comprising the first memory block and the second memory block; and
a storage controller configured to write the first data to the first memory block and write the second data to the second memory block,
wherein the storage controller comprises:
a write amplification (WAF) manager comprising an open memory cell detector configured to check whether an open memory cell exists in the first memory block or the second memory block before an Nth programming of the first memory block and the second memory block is performed, and a memory cell compactor configured to conduct memory cell compaction by moving a location of an (N−1)th-programming of a memory cell in one memory block of the first memory block and the second memory block to a memory cell in the other memory block of the first memory block and the second memory block when the open memory cell exists in the first memory block or the second memory block; and
a central processing unit (CPU) configured to not perform the Nth programming of the first memory block and the second memory block after the memory cell compactor conducts the memory cell compaction.

### Claim 16 (depends on 15)

The storage device of claim 15, wherein the memory cell compaction is conducted by moving the location of the (N−1)th-programming of the memory cell to a memory block having fewer open memory cells.

### Claim 17 (depends on 16)

The storage device of claim 16, wherein the memory cell whose (N−1)th-programming location is moved is a memory cell existing on a word line of a same order in the first memory block and the second memory block.

### Claim 18 (depends on 15)

The storage device of claim 15, wherein the open memory cell is an empty memory cell of a last word line that is (N−1)th programmed in the first memory block or the second memory block.

### Claim 19 (depends on 18)

The storage device of claim 18, wherein, when the open memory cell does not exist, the memory cell compaction is not conducted.

### Claim 20 (depends on 15)

The storage device of claim 15, wherein the NVM device further comprises a third memory block and the storage controller writes third data to the third memory block by performing programming of the third memory block N-times, and
wherein the open memory cell detector is configured to detect the open memory cell existing in the first memory block and the second memory block before the storage controller performs an Nth programming of the third memory block.