# US 12,014,771 B2 · Method of pseudo-triple-port SRAM datapaths

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- Number: US 12,014,771 B2
- Document ID: US12014771B2
- Status: Granted
- Kind: B2
- Application number: 18/175,023
- Filed: 2023-02-27
- Published: 2023-07-13
- Granted: 2024-06-18
- Earliest claimed: 2020-09-22
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Changho Jung; Arun Babu Pallerla; Chulmin Jung
- Web page: https://patentgrep.com/patent/US12014771B2

## CPC

- G11C 11/418: Address circuits
- G11C 11/419: Read-write [R-W] circuits
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

## Claims

### Claim 1

A method for a memory, comprising:
in a read cycle responsive to a beginning of a cycle memory clock signal, performing a first single-ended read through a first bit line to a first bitcell in a column to charge the first bit line to a power supply voltage;
while performing the first single-ended read, performing a second single-ended read through a second bit line to a second bitcell in the column to discharge the second bit line; and
in a write cycle following the read cycle, writing to the first bitcell through the first bit line and through the second bit line, wherein the first bit line remains charged to the power supply voltage from an end of the read cycle to an end of the write cycle and the second bit line remains discharged from the end of the read cycle to the end of the write cycle.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
asserting a first word line coupled to the first bitcell during the read cycle while de-asserting a second word line coupled to the first bitcell; and
asserting a second word line coupled to the second bitcell during the read cycle while de-asserting a first word line coupled to the second bitcell.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
asserting the first word line coupled to the first bitcell during the write cycle; and
asserting the second word line coupled to the first bitcell during the write cycle.

### Claim 4 (depends on 1)

The method of claim 1, wherein the read cycle and the write cycle both occur during a single cycle of the memory clock signal.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
driving a first global read bit line with a first bit decision from the single-ended read to the first bitcell; and
driving a second global read bit lie with a second bit decision from the single-ended read to the second bitcell.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
forming the first bit decision by inverting a voltage for the first bit line; and
forming the second bit decision by inverting a voltage for the second bit line.

### Claim 7 (depends on 5)

The method of claim 5, wherein driving the first global read bit line with the first bit decision comprises processing a voltage for the first bit line through a first NAND gate, and wherein driving the second global read bit line with the second bit decision comprises processing a voltage for the second bit line through a second NAND gate.