# US 12,014,770 B2 · Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein

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- Number: US 12,014,770 B2
- Document ID: US12014770B2
- Status: Granted
- Kind: B2
- Application number: 17/649,342
- Filed: 2022-01-28
- Published: 2022-09-15
- Granted: 2024-06-18
- Earliest claimed: 2017-10-17
- Assignees: R&D3 LLC
- Applicants: R&D 3 LLC
- Inventors: Ravindraraj Ramaraju
- Web page: https://patentgrep.com/patent/US12014770B2

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/08: Control thereof
- G11C 7/1036: {using data shift registers}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/4045: {using a plurality of serially connected access transistors, each having a storage capacitor}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/565: {using capacitive charge storage elements}
- G11C 16/30: Power supply circuits
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- G11C 11/4094: Bit-line management or control circuits
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

## Claims

### Claim 1

A memory device comprising:
a plurality of memory cells, each memory cell having at least two data values, and each memory cell having an effective variable impedance that varies in accordance with a respective data value stored for each data value therein;
a plurality of tracking memory cells having a predetermined effective impedance in accordance with a respective data value stored therein; and
a read circuit configured to read an effective data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell with respect to the predetermined impedance of a selected tracking memory cell, wherein the effective data value corresponds to a plurality of bits.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein:
each respective data value corresponds to a plurality of bits.

### Claim 3 (depends on 1)

The memory device according to claim 1, wherein:
the variable impedance comprises a variable current.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein:
the variable impedance of each memory cell arises from a transistor within the cell whose gate voltage varies with the data written thereto.

### Claim 5 (depends on 4)

The memory device according to claim 4, wherein:
the plurality of memory cells comprises volatile memory cells.

### Claim 6 (depends on 4)

The memory device according to claim 4, wherein:
the plurality of memory cells comprises non-volatile memory cells.

### Claim 7 (depends on 4)

The memory device according to claim 4, wherein:
each memory cell comprises more than one transistor whose respective gate voltage varies with the data written thereto; and
said more than one transistor together determine the variable impedance of the memory cell.

### Claim 8 (depends on 1)

The memory device according to claim 1, wherein:
the signal node comprises a read bit line node.

### Claim 9 (depends on 1)

The memory device according to claim 1, wherein:
the read circuit, together with a selection circuit, is configured to effect a change in voltage of the signal node at a variable rate corresponding to the variable impedance of the selected memory cell, and to read the data value stored within the selected memory cell based upon the variable time delay determination of the signal node voltage change.

### Claim 10 (depends on 9)

The memory device according to claim 9, wherein:
the read circuit is configured to discharge the signal node at a variable rate corresponding to the impedance of the selected memory cell;
the variable time delay determination of the signal node voltage change comprises a time-to-discharge measurement of the signal node voltage change; and
the signal node comprises a read bit line node.

### Claim 11 (depends on 9)

The memory device according to claim 9, wherein:
the read circuit is configured to charge the signal node at a variable rate corresponding to the variable impedance of the selected memory cell;
the variable time delay determination of the signal node comprises a time-to-charge measurement of the signal node; and
the signal node comprises a read bit line node.

### Claim 12

A memory device comprising:
a plurality of memory cells in an array, each memory cell having at least two data values;
a plurality of tracking cells in the array with a predetermined data value; and
a read circuit configured to effect a voltage transition of a signal node at a variable rate corresponding to a data value stored within a selected memory cell, and to perform a time-to-transition measurement of the signal node to determine an effective data value stored within the selected memory cell with respect to the predetermined data value stored within a selected tracking cell, wherein the effective data value corresponds to a plurality of bits.

### Claim 13 (depends on 12)

The memory device according to claim 12, wherein:
each respective data value corresponds to a plurality of bits.

### Claim 14 (depends on 12)

The memory device according to claim 12, wherein:
the variable impedance of each memory cell arises from a transistor within the cell whose gate voltage varies with the data written thereto.

### Claim 15 (depends on 14)

The memory device according to claim 14, wherein:
the plurality of memory cells comprises volatile memory cells.

### Claim 16 (depends on 14)

The memory device according to claim 14, wherein:
each memory cell comprises more than one transistor whose gate voltage varies with the data written thereto; and
said more than one transistor together determine the variable impedance of the memory cell.

### Claim 17 (depends on 12)

The memory device according to claim 12, wherein:
the read circuit is further configured to perform, before selecting the selected memory cell, a calibration time-to-transition measurement of the signal node to calibrate a reference condition of the signal node; and
the read circuit is further configured to compare the time-to-transition measurement against the calibration time-to-transition measurement to determine the data value stored in the selected memory cell.

### Claim 18 (depends on 12)

The memory device according to claim 12, wherein the read circuit comprises:
a time-to-discharge measurement circuit having an input coupled to the signal node, and having a delay line that includes a plurality of delay stages, each coupled to a respective one of a plurality of registers that are responsive to a common strobe clock.

### Claim 19 (depends on 18)

The memory device according to claim 18, wherein the time-to-discharge measurement circuit further comprises:
an input stage having an input coupled to the signal node, and having an output coupled to the delay line, said input stage configured to generate a timing signal on its output when the signal node has fallen to a predetermined percentage of its initial voltage.

### Claim 20 (depends on 19)

The memory device according to claim 19, wherein:
the signal node comprises a read bit line node; and
each respective data value corresponds to a plurality of bits.