# US 12,014,769 B2 · Volatile memory device

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- Number: US 12,014,769 B2
- Document ID: US12014769B2
- Status: Granted
- Kind: B2
- Application number: 17/876,046
- Filed: 2022-07-28
- Published: 2023-05-11
- Granted: 2024-06-18
- Earliest claimed: 2021-11-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jae Pil Lee; Hi Jung Kim; Kwang Sook Noh
- Web page: https://patentgrep.com/patent/US12014769B2

## CPC

- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 11/4099: Dummy cell treatment; Reference voltage generators
- G11C 11/419: Read-write [R-W] circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A volatile memory device may include; a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier in a first direction, a first mat disposed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, a third sense amplifier spaced apart from the second sense amplifier in a second direction, a fourth sense amplifier spaced apart from the third sense amplifier in the first direction, and a second mat disposed between the third sense amplifier and the fourth sense amplifier and including a first complementary bit line connected to the first sense amplifier.

## Claims

### Claim 1

A volatile memory device comprising:
a first sense amplifier;
a second sense amplifier spaced apart from the first sense amplifier in a first direction;
a first mat disposed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier;
a third sense amplifier spaced apart from the second sense amplifier in a second direction;
a fourth sense amplifier spaced apart from the third sense amplifier in the first direction; and
a second mat disposed between the third sense amplifier and the fourth sense amplifier and including a first complementary bit line connected to the first sense amplifier.

### Claim 2 (depends on 1)

The volatile memory device of claim 1, wherein the first sense amplifier is configured to perform a read/write operation on a first memory cell connected to the first bit line using the first complementary bit line.

### Claim 3 (depends on 1)

The volatile memory device of claim 1, further comprising:
a metal line connecting the first sense amplifier with the first complementary bit line.

### Claim 4 (depends on 1)

The volatile memory device of claim 1, further comprising:
a first word line connected to the first bit line and the second bit line of the first mat;
a second word line connected to the first complementary bit line of the second mat; and
a metal line connecting the first sense amplifier with the first complementary bit line, wherein the metal line is formed under the first and second word lines.

### Claim 5 (depends on 4)

The volatile memory device of claim 4, wherein the metal line is formed under the first mat.

### Claim 6 (depends on 1)

The volatile memory device of claim 1, further comprising:
a fifth sense amplifier spaced apart from the first sense amplifier in the second direction; and
a third mat disposed between the fifth sense amplifier and the third sense amplifier and including a third bit line connected to the third sense amplifier and a fourth bit line connected to the fifth sense amplifier.

### Claim 7 (depends on 6)

The volatile memory device of claim 6, further comprising:
a dummy bit line disposed in a direction opposite to the first direction from the fifth sense amplifier and connected to the fifth sense amplifier.

### Claim 8 (depends on 6)

The volatile memory device of claim 6, further comprising:
a sixth sense amplifier spaced apart from the second sense amplifier in the first direction; and
a fourth mat disposed between the second sense amplifier and the sixth sense amplifier and including a fourth complementary bit line connected to the fifth sense amplifier.

### Claim 9 (depends on 8)

The volatile memory device of claim 8, wherein the fifth sense amplifier is configured to perform a read/write operation on a fourth memory cell connected to the fourth bit line using the fourth complementary bit line.

### Claim 10 (depends on 8)

The volatile memory device of claim 8, further comprising:
a metal line connecting the fifth sense amplifier with the fourth complementary bit line.

### Claim 11 (depends on 1)

The volatile memory device of claim 1, wherein the first complementary bit line is connected to the fourth sense amplifier.

### Claim 12

A volatile memory device comprising:
a row decoder extending in a first direction;
a column decoder extending in a second direction; and
a memory cell array between the row decoder and the column decoder,
wherein the memory cell array includes:
a center region including a first sense amplifier, a first mat including a first bit line connected to the first sense amplifier, and a second mat including a first complementary bit line connected to the first sense amplifier; and
a first edge region disposed in the first direction from the center region,
wherein the first edge region includes a second sense amplifier and a third mat including a second bit line connected to the second sense amplifier and disposed in a third direction opposite to the first direction from the second sense amplifier, and
the second sense amplifier is connected to the first complementary bit line of the center region.

### Claim 13 (depends on 12)

The volatile memory device of claim 12, wherein the memory cell array comprises a second edge region disposed in the third direction from the center region,
the center region includes a third sense amplifier, a third mat including a third bit line connected to the third sense amplifier and a fourth mat including a third complementary bit line connected to the third sense amplifier,
the second edge region includes a fourth sense amplifier, and a fourth mat disposed in the first direction from the fourth sense amplifier and including a fourth bit line connected to the fourth sense amplifier, and
the fourth sense amplifier is connected to the third complementary bit line of the center region.

### Claim 14 (depends on 12)

The volatile memory device of claim 12, wherein the first sense amplifier is configured to perform a read/write operation on a first memory cell connected to the first bit line using the first complementary bit line, and
the second sense amplifier is configured to perform a read/write operation on a second memory cell connected to the second bit line using the first complementary bit line.

### Claim 15 (depends on 12)

The volatile memory device of claim 12, wherein the memory cell array includes:
a plurality of word lines connected to the first mat, the second mat, and the third mat; and
a metal line connecting the second sense amplifier with the first complementary bit line, wherein the metal line is formed under the word lines.

### Claim 16 (depends on 12)

The volatile memory device of claim 12, wherein the first edge region includes:
a third sense amplifier disposed in the second direction from the second sense amplifier; and
a third bit line disposed in the third direction from the third sense amplifier and connected to the third sense amplifier.

### Claim 17 (depends on 16)

The volatile memory device of claim 16, wherein the first edge region includes a dummy bit line extending in the first direction from the third sense amplifier and connected to the third sense amplifier.

### Claim 18

A volatile memory device comprising:
a first sense amplifier;
a second sense amplifier spaced apart from the first sense amplifier in a first direction;
a third sense amplifier spaced apart from the first sense amplifier in the first direction and spaced apart from the second sense amplifier in a second direction;
a first mat formed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier;
a second mat formed between the first sense amplifier and the third sense amplifier and including a first complementary bit line connected to the first sense amplifier and a third bit line connected to the third sense amplifier;
a third mat spaced apart from the second sense amplifier in the first direction and including a second complementary bit line connected to the second sense amplifier;
a fourth mat spaced apart from the third sense amplifier in the first direction and including a third complementary bit line connected to the third sense amplifier;
a first word line connected to the first mat and the fourth mat; and
a second word line connected to the second mat and the third mat.

### Claim 19 (depends on 18)

The volatile memory device of claim 18, wherein the first word line includes a first sub word line connected to the first and second bit lines of the first mat, a second sub word line connected to the third complementary bit line of the fourth mat, and a first metal line connecting the first sub word line and the second sub word line.

### Claim 20 (depends on 19)

The volatile memory device of claim 19, wherein the first metal line is formed in a substrate under the first sub word line and the second sub word line.