# US 12,014,767 B2 · Double data rate (DDR) memory controller apparatus and method

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- Number: US 12,014,767 B2
- Document ID: US12014767B2
- Status: Granted
- Kind: B2
- Application number: 18/208,050
- Filed: 2023-06-09
- Published: 2024-04-04
- Granted: 2024-06-18
- Earliest claimed: 2008-06-06
- Assignees: Uniquify, Inc.
- Applicants: Uniquify, Inc.
- Inventors: Mahesh Gopalan; David Wu; Venkat Iyer
- Web page: https://patentgrep.com/patent/US12014767B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 1/14: Time supervision arrangements, e.g. real time clock
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/065: {Replication mechanisms}
- G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}
- G06F 12/0646: {Configuration or reconfiguration}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/4243: {with synchronous protocol}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 29/022: {in I/O circuitry}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 11/40: using transistors
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

## Claims

### Claim 1

A double data rate memory controller for self-calibration, the controller comprising:
a data capture register configured to be implemented in a byte lane of a physical clocking domain (phy-domain), configured to be clocked by a delayed version of a strobe signal, and further configured to generate, in response to receiving read data that has not passed through a delay element, a first output in the phy-domain;
a first core domain register coupled the data capture register to receive the first output in a core clock domain;
a phy-domain delay element configured to generate the delayed version of the strobe signal to clock the data capture register;
a first core clock delay element coupled to the first core domain register, the first core clock delay element configured to generate a capture clock signal, represents a delayed version of a core clock signal, to clock the first core domain register; and
a second core domain register coupled to the first core domain register and configured to generate, in response to being clocked by the core clock signal, a second output.

### Claim 2 (depends on 1)

The controller of claim 1, wherein at least one of the phy-domain delay element or the first core clock delay element is programmable.

### Claim 3 (depends on 1)

The controller of claim 1, further comprising a self-configuring logic (SCL) circuit that is communicatively coupled to the phy-domain delay element and the first core clock delay element.

### Claim 4 (depends on 3)

The controller of claim 3, wherein the SCL circuit is configured to perform steps comprising at least one of determining a delay amount for the first core clock delay element or determining a delay amount for the phy-domain delay element.

### Claim 5 (depends on 4)

The controller of claim 4, wherein the SCL circuit is configured to adjust the delay amount for the core clock delay such that the capture clock signal clocks the first core domain register on an active edge of the capture clock signal, thereby reducing a latency of the read data when the read data is transferred from the phy-domain to the core clock domain.

### Claim 6 (depends on 4)

The controller of claim 4, wherein the delay amount adjusts the delayed version of the core clock signal relative to the delayed version of the strobe signal.

### Claim 7 (depends on 4)

The controller of claim 4, wherein at least one of the delay amount for the first core clock delay element or the delay amount for the phy-domain delay element is determined by at least one of an initialization event or a calibration event.

### Claim 8 (depends on 4)

The controller of claim 4, wherein the SCL circuit is configured to adjust the delay amount for the first core clock delay element such that the capture clock signal captures the read data within a passing window.

### Claim 9 (depends on 8)

The controller of claim 8, wherein the passing window is defined by a relationship between the core clock and the delayed version of the strobe signal.

### Claim 10 (depends on 9)

The controller of claim 9, wherein the passing window is defined by a relationship between an active edge of the core clock signal and a transition of the read data.

### Claim 11 (depends on 10)

The controller of claim 10, wherein the SCL is configured to cause the controller to perform a dynamic calibration during a normal circuit operation.

### Claim 12 (depends on 11)

The controller of claim 11, wherein the dynamic calibration compensates for at least one of a system timing irregularity or an environmental parameter.

### Claim 13 (depends on 11)

The controller of claim 11, wherein the dynamic calibration is performed at one half of a frequency of that of the strobe signal.

### Claim 14 (depends on 11)

The controller of claim 11, wherein the dynamic calibration uses test data that has been stored in a register.

### Claim 15 (depends on 14)

The controller of claim 14, wherein the test data comprises a passing criterion associated with a minimum number of delay elements associated with a successful data capture.

### Claim 16 (depends on 10)

The controller of claim 10, further comprising:
second and third core clock delay elements that each receives the core clock signal and is communicatively coupled to the SCL;
a first flip-flop coupled to the second core clock delay element, the first flip-flop samples the delay amount for the phy-domain delay element and outputs a first flip-flop output; and
a second flip-flop coupled to the third core clock delay element, the second flip-flop samples the delay amount for the first core clock delay element and outputs a second flip-flop output.

### Claim 17 (depends on 16)

The controller of claim 16, wherein the SCL, in response to receiving the second output, the first flip-flop output, and the second flip-flop output, controls one or more input lines of a multiplexer.

### Claim 18 (depends on 1)

The controller of claim 1, wherein the read data is obtained in the phy-domain from a memory device.

### Claim 19 (depends on 1)

The controller of claim 1, further comprising a clock generator that is phase-synchronized and frequency-synchronized with the strobe signal.

### Claim 20 (depends on 1)

The controller of claim 1, wherein the capture clock signal determines when the read data enters the core domain, and the core clock signal clocks the second output.