# US 12,014,763 B2 · Magnetic junction memory device and writing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,014,763 B2 - Document ID: US12014763B2 - Status: Granted - Kind: B2 - Application number: 17/882,790 - Filed: 2022-08-08 - Published: 2022-11-24 - Granted: 2024-06-18 - Earliest claimed: 2019-07-22 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chan Kyung Kim; Ji Yean Kim; Hyun Taek Jung; Ji Eun Kim; Tae Seong Kim; Sang-Hoon Jung; Jae Wook Joo - Web page: https://patentgrep.com/patent/US12014763B2 ## CPC - G11C 11/1675: {Writing or programming circuits or methods} - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 11/1655: {Bit-line or column circuits} - G11C 11/1657: {Word-line or row circuits} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines. ## Claims ### Claim 1 A writing method of a magnetic junction memory device which writes data to first and second magnetic junction memory cells using a global write driver and first and second local write drivers, the writing method comprising: receiving, by the global write driver, a first write command and first write data from a host; storing the first write data in a first write latch of the first local write driver in response to the first write command while the global write driver is receiving a second write command and second write data from the host, writing, by the first local write driver, the first write data to the first magnetic junction memory cell in response to the first write command while the global write driver is receiving the second write command and the second write data from the host; and writing, by the first local write driver, the first write data to the first magnetic junction memory cell in response to the first write command while the second local write driver is storing the second write data in second write latch of the second local write driver and writing the second write data to the second magnetic junction memory cell in response to the second write command. ### Claim 2 (depends on 1) The writing method of claim 1, further comprising: receiving, by the global write driver, a third write command and third write data from the host while the second local write driver is writing the second write data to the second magnetic junction memory cell in response to the second write command. ### Claim 3 (depends on 1) The writing method of claim 1, wherein the writing, by the first local write driver, the first write data to the first magnetic junction memory cell in response to the first write command, comprises receiving the first write data from the global write driver via a global data line, storing the first write data, and writing the stored first write data to the first magnetic junction memory cell via a local data line, which is separate from the global data line. ### Claim 4 (depends on 1) The writing method of claim 1, wherein the magnetic junction memory device further includes a third local write driver and a third magnetic junction memory cell, and the writing method further comprises receiving, by the global write driver, a third write command and third write data while the second local write driver is writing the second write data to the second magnetic junction memory cell in response to the second write command, and writing, by the second local write driver, the second write data to the second magnetic junction memory cell while the third local write driver is writing the third write data to the third magnetic junction memory cell in response to the third write command. ### Claim 5 (depends on 1) The writing method of claim 1, wherein the first magnetic junction memory cell is disposed in a first memory bank, the second magnetic junction memory cell is disposed in a second memory bank, and the first local write driver is disposed between the first and second memory banks. ### Claim 6 (depends on 1) The writing method of claim 1, wherein the host is external to the memory device. ### Claim 7 A magnetic junction memory device comprising: a first memory bank including a plurality of first magnetic junction memory cells; a first local write driver adjacent to the first memory bank and connected to first and second global data lines, the first local write driver configured to write data to the plurality of first magnetic junction memory cells via first and second local data lines; a second memory bank adjacent to the first memory bank and including a plurality of second magnetic junction memory cells; a second local write driver adjacent to the second memory bank and connected to the first and second global data lines, the second local write driver configured to write data to the plurality of second magnetic junction memory cells via third and fourth local data lines, the third and fourth local data lines not connected to the first and second local data lines; a global write driver configured to provide first write data to the first local write driver via the first and second global data lines and provide second write data to the second local write driver via the first and second global data lines; a column decoder connected to the first memory bank and the second memory bank; and a sensing circuit configured to read data from the first memory bank and the second memory bank, wherein during a first write period, the global write driver is configured to receive the second write data from a host and the first local write driver is configured to receive the first write data from the global write driver and write the first write data to the plurality of first magnetic junction memory cells, during a second write period, which follows the first write period, the global write driver is configured to receive a third write data from the host and the second local write driver is configured to receive the second write data from the global write driver and write the second write data to the plurality of second magnetic junction memory cells, the first memory bank includes a first sub-memory cell array which include the plurality of first magnetic junction memory cells, the second memory bank includes a second sub-memory cell array which includes the plurality of second magnetic junction memory cells, which does not share wordlines with the first sub-memory cell array, the first local write driver is between the first and second sub-mirror cell arrays, the first local write driver includes a first write latch configured to store the first write data to be written to the plurality of first magnetic junction memory cells, and the second local write driver includes a second write latch configured to store the cells and which is separate from the first write latch. ### Claim 8 (depends on 7) The magnetic junction memory device of claim 7, wherein during the second write period, the first local write driver is configured to write the first write data to the plurality of first magnetic junction memory cells. ### Claim 9 (depends on 8) The magnetic junction memory device of claim 8, further comprising: a third memory bank adjacent to the second memory bank and including a plurality of third magnetic junction memory cells; and a third local write driver adjacent to the third memory bank and connected to the first and second global data lines, the third local write driver configured to write data to the plurality of third magnetic junction memory cells via fifth and sixth local data lines, the fifth and sixth local data lines not connected to the first, second, third and fourth local data lines, wherein during a third write period, which follows the second write period, the global write driver is configured to receive a fourth write data from the host and the third local write driver is configured to receive the third write data from the global write driver and write the third write data to the plurality of third magnetic junction memory cells. ### Claim 10 (depends on 9) The magnetic junction memory device of claim 9, wherein during the third write period, the second local write driver is configured to write the second write data to the plurality of second magnetic junction memory cells. ### Claim 11 (depends on 7) The magnetic junction memory device of claim 7, further comprising: a first sub-memory cell array selection element configured to connect the first global data line and the first local data line based on a bank selection control signal, and configured to connect the second global data line and the second local data line based on a bank selection control signal; and a second sub-memory cell array selection element configured to connect the first global data line and the third local data line based on a bank selection control signal and configured to connect the second global data line and the fourth local data line based on the bank selection control signal. ### Claim 12 (depends on 7) The magnetic junction memory device of claim 7, further comprising: a first bitline multiplexer configured to select the first and second local data lines; and a second bitline multiplexer configured to select the third and fourth local data lines. ### Claim 13 (depends on 7) The magnetic junction memory device of claim 7, wherein the first local data line is connected to first ends of each of the plurality of first magnetic junction memory cells, and the second local data line is connected to second ends of each of the plurality of first magnetic junction memory cells. ### Claim 14 (depends on 13) The magnetic junction memory device of claim 13, wherein the first global data line includes a global source line, the second global data line includes a global bitline, the first and third local data lines include first and third local source lines which are connected to the global source line, and the second and fourth local data lines include second and fourth local bitlines which are connected to the global bitline. ### Claim 15 A magnetic junction memory device comprising: a global write driver configured to receive a first write command from a host for a first memory bank, which includes a plurality of first magnetic junction memory cells, during a first write period, receive a second write command from the host for a second memory bank, which includes a plurality of second magnetic junction memory cells, during a second write period, the second write period following the first write period and receive a third write command from the host for a third memory bank, which includes a plurality of third magnetic junction memory cells, during a third write period, the third write period following the second write period; a first local write driver configured to receive the first write command from the global write driver and perform a first write operation on the plurality of first magnetic junction memory cells during the second write period; a second local write driver configured to receive the second write command from the global write driver and perform a second write operation on the plurality of second magnetic junction memory cells during the third write period; a column decoder connected to the first memory bank and the second memory bank; a sensing circuit configured to read data from the first memory bank and the second memory bank; a first write latch configured to receive first write data from the global write driver during the second write period; and a second write latch configured to receive second write data from the global write driver during the third write period, wherein the second write latch is separate from the first write latch, wherein during the third write period, the first local write driver is configured to perform the first write operation on the plurality of first magnetic junction memory cells based on the first write command. ### Claim 16 (depends on 15) The magnetic junction memory device of claim 15, further comprising: a third local write driver, wherein the global write driver is configured to receive a third write command for a third memory bank, which includes a plurality of third magnetic junction memory cells, during a fourth write period, which follows the third write period, the third local write driver is configured to receive the third write command from the global write driver and perform a third write operation on the plurality of third magnetic junction memory cells, and during the fourth write period, the second local write driver is configured to perform the second write operation on the plurality of second magnetic junction memory cells based on the second write command. ### Claim 17 (depends on 16) The magnetic junction memory device of claim 16, wherein during the third write period, the global write driver is configured to receive the third write command. ### Claim 18 (depends on 16) The magnetic junction memory device of claim 16, further comprising: a fourth local write driver, wherein the global write driver is configured to receive a fourth write command for a fourth memory bank, which includes a plurality of fourth magnetic junction memory cells, during a fifth write period, which follows the fourth write period, the fourth local write driver is configured to receive the fourth write command from the global write driver and perform a fourth write operation on the plurality of fourth magnetic junction memory cells, and during the fifth write period, the third local write driver is configured to perform the third write operation on the plurality of third magnetic junction memory cells based on the third write command.