# US 12,014,762 B2 · Semiconductor memory device with spin-orbit coupling channel

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- Number: US 12,014,762 B2
- Document ID: US12014762B2
- Status: Granted
- Kind: B2
- Application number: 17/814,057
- Filed: 2022-07-21
- Published: 2023-04-13
- Granted: 2024-06-18
- Earliest claimed: 2021-10-12
- Assignees: Samsung Electronics Co., Ltd.; National University of Singapore
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Rahul Mishra; Hyunsoo Yang; Ung Hwan Pi
- Web page: https://patentgrep.com/patent/US12014762B2

## CPC

- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/18: using Hall-effect devices
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 52/80: Constructional details
- H10N 52/85: Materials of the active region
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor memory device may be provided. The semiconductor memory device may include data storage patterns having respective first sides and respective second sides, a spin-orbit coupling (SOC) channel layer in common contact with the first sides of the data storage patterns, the SOC channel layer is configured to provide a spin-orbit torque to the data storage patterns, read access transistors connected between the second sides of respective ones of the data storage patterns and respective data lines, a write access transistor connected between a first end of the SOC channel layer and a source line, and a bit line connected to a second end of the SOC channel layer. Each of the data storage patterns comprises a free layer in contact with the SOC channel layer and an oxygen reservoir layer in contact with the free layer.

## Claims

### Claim 1

A semiconductor memory device, comprising:
data storage patterns having respective first sides and respective second sides;
a spin-orbit coupling (SOC) channel layer in common contact with the first sides of the data storage patterns, wherein the SOC channel layer is configured to provide a spin-orbit torque to the data storage patterns;
read access transistors connected between the second sides of respective ones of the data storage patterns and respective data lines;
a write access transistor connected between a first end of the SOC channel layer and a source line; and
a bit line connected to a second end of the SOC channel layer,
wherein each of the data storage patterns comprises a free layer in contact with the SOC channel layer and an oxygen reservoir layer in contact with the free layer.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the oxygen reservoir layer comprises a rare-earth element.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the oxygen reservoir layer comprises a gadolinium oxide (GdOx) layer.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein a thickness of the oxygen reservoir layer is greater than a thickness of the SOC channel layer or a thickness of the free layer.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1,
wherein the oxygen reservoir layer is between a fixed layer and the free layer, and
wherein the oxygen reservoir layer is spaced apart from the SOC channel layer.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein each of the data storage patterns further comprises a fixed layer on the oxygen reservoir layer.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein each of the data storage patterns further comprises a first tunnel magnetoresistance (TMR) enhancement layer between the free layer and the oxygen reservoir layer.

### Claim 8 (depends on 7)

The semiconductor memory device of claim 7, wherein each of the data storage patterns further comprises a second TMR enhancement layer between the oxygen reservoir layer and the fixed layer.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein the oxygen reservoir layer comprises an oxide material configured to cause migration of an oxygen ion when a voltage is applied thereto.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein each of the data storage patterns is configured such that an amount of oxygen in an interface region between the free layer and the SOC channel layer is adjusted by a voltage applied thereto.