# US 12,010,933 B2 · Via structure and methods of forming the same

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- Number: US 12,010,933 B2
- Document ID: US12010933B2
- Status: Granted
- Kind: B2
- Application number: 17/977,317
- Filed: 2022-10-31
- Published: 2023-02-23
- Granted: 2024-06-11
- Earliest claimed: 2017-11-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Chieh Huang; Jieh-Jang Chen; Feng-Jia Shiu; Chern-Yow Hsu
- Web page: https://patentgrep.com/patent/US12010933B2

## CPC

- H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/432: {using selective deposition}
- H10P 50/73: {using masks for insulating materials}
- H10P 52/403: {of conductive or resistive materials}
- H10P 95/062: {involving a dielectric removal step}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

## Claims

### Claim 1

A method comprising:
forming a first dielectric layer over a first electrode layer;
forming a patterned second dielectric layer over the first dielectric layer;
forming a sacrificial layer on the patterned second dielectric layer;
forming a trench through the sacrificial layer that exposes the first electrode layer;
forming a conductive material in the trench; and
after forming the conductive material in the trench, removing at least a first portion of the sacrificial layer and at least a first portion of the patterned second dielectric layer to expose a portion of the first dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a phase-changing material layer on the conductive material; and
forming a second electrode layer on the phase-changing material.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming a hard mask layer directly on the sacrificial layer prior to forming the trench through the sacrificial layer that exposes the first electrode layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the forming of the trench through the sacrificial layer that exposes the first electrode layer includes removing a first portion of the hard mask layer, a second portion of the sacrificial layer and a second portion of the first dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the sacrificial layer is formed of a dielectric material that has the same composition as the patterned second dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the sacrificial layer is formed of a dielectric material that has a different composition than the patterned second dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming of the sacrificial layer on the patterned second dielectric layer includes forming the sacrificial layer directly on the patterned second dielectric layer and the first dielectric layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein a top surface of the conductive material is substantially coplanar with a top surface of the first dielectric layer after the removing of at least the first portion of the sacrificial layer and at least the first portion of the patterned second dielectric layer to expose the portion of the first dielectric layer.

### Claim 9

A method comprising:
providing a substrate having a first conductive feature disposed therein;
forming a first dielectric layer on the first conductive feature;
forming a patterned second dielectric layer on the first dielectric layer;
forming a third dielectric layer on the patterned second dielectric layer;
forming an opening through the third dielectric layer to the first conductive feature;
forming a first conductive material in the opening directly on the first conductive feature; and
performing a planarization process on the first conductive material, the third dielectric layer, and the patterned second dielectric layer to expose a top surface of the first dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein a portion of the first conductive material is disposed within the first dielectric layer and in physical contact with the first conductive feature after the performing of the planarization process.

### Claim 11 (depends on 9)

The method of claim 9, wherein the patterned second dielectric layer includes a plurality of segments that are spaced apart from each other and at least partially surround the first conductive feature in a top view.

### Claim 12 (depends on 9)

The method of claim 9, wherein the forming of the first dielectric layer on the first conductive feature includes forming the first dielectric layer directly on the first conductive feature.

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming a semiconductor material layer directly on the first conductive material after the performing of the planarization process.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming a second conductive material directly on the semiconductor layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
patterning the second conductive material and the semiconductor material layer; and
forming a second dielectric layer directly on the patterned second conductive material and the patterned semiconductive material layer.

### Claim 16

A method comprising:
providing a first electrode layer;
forming a first material layer on the first electrode layer;
forming a second material layer on the first material layer;
patterning the second material layer to form a first segment and a second segment of the second material layer;
forming a third material layer on the first and second segments of the second material layer such that the first and second segments of the second material layer are at least partially disposed within the third material layer;
forming a conductive feature through the first and second segments of the second material layer to the first electrode layer;
removing the third material layer, a first portion of the conductive feature and the first and second segments of the second material layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein a second portion of the conductive feature is disposed within the first material layer and in physical contact with the first electrode layer after the removing of the third material layer, the first portion of the conductive feature and the first and second segments of the second material layer.

### Claim 18 (depends on 16)

The method of claim 16, further comprising forming a phase-changing material directly on a second portion of the conductive feature that remains after the removing of the third material layer, the first portion of the conductive feature and the first and second segments of the second material layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming a second electrode layer directly on the phase-changing material.

### Claim 20 (depends on 16)

The method of claim 16, wherein the second material layer is formed of a different material than the third material layer.