# US 12,010,931 B2 · Resistive random-access memory (RRAM) device and forming method thereof

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- Number: US 12,010,931 B2
- Document ID: US12010931B2
- Status: Granted
- Kind: B2
- Application number: 17/196,979
- Filed: 2021-03-09
- Published: 2022-08-04
- Granted: 2024-06-11
- Earliest claimed: 2021-02-01
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chia-Ching Hsu; Wang Xiang; Shen-De Wang
- Web page: https://patentgrep.com/patent/US12010931B2

## CPC

- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/841: {Electrodes}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.

## Claims

### Claim 1

A resistive random-access memory (RRAM) device, comprising:
a bottom electrode line directly on a first metal structure;
a top electrode island disposed beside the bottom electrode line;
a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island; and
a second metal structure directly contacting the resistive material and the top electrode island.

### Claim 2 (depends on 1)

The resistive random-access memory (RRAM) device according to claim 1, further comprising:
a dielectric layer disposed on the bottom electrode lines, wherein the resistive material penetrates through the dielectric layer.

### Claim 3 (depends on 2)

The resistive random-access memory (RRAM) device according to claim 2, wherein the dielectric layer comprises a silicon nitride layer.

### Claim 4 (depends on 1)

The resistive random-access memory (RRAM) device according to claim 1, wherein the resistive material comprises transition-metal-oxide (TMO).

### Claim 5 (depends on 1)

The resistive random-access memory (RRAM) device according to claim 1, further comprising:
a cap layer between the first metal structure and the bottom electrode line.

### Claim 6 (depends on 5)

The resistive random-access memory (RRAM) device according to claim 5, wherein the cap layer has openings for the bottom electrode line physically connecting to the first metal structure.

### Claim 7 (depends on 5)

The resistive random-access memory (RRAM) device according to claim 5, wherein the cap layer comprises a nitrogen containing silicon carbide (SiCN) layer.

### Claim 8 (depends on 1)

The resistive random-access memory (RRAM) device according to claim 1, wherein the resistive material has a U-shape cross-sectional profile.

### Claim 9 (depends on 1)

The resistive random-access memory (RRAM) device according to claim 1, wherein the top electrode island has an I-shape cross-sectional profile or a T-shape cross-sectional profile.

### Claim 10 (depends on 1)

The resistive random-access memory (RRAM) device according to claim 1, further comprising:
a via disposed beside the RRAM cell, wherein two ends of the via contact the first metal structure and the second metal structure respectively.