# US 12,010,930 B2 · Wrap-around projection liner for AI device

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- Number: US 12,010,930 B2
- Document ID: US12010930B2
- Status: Granted
- Kind: B2
- Application number: 17/470,003
- Filed: 2021-09-09
- Published: 2023-03-09
- Granted: 2024-06-11
- Earliest claimed: 2021-09-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Injo Ok; Hsueh-Chung Chen; Mary Claire Silvestre; Yann Mignot
- Web page: https://patentgrep.com/patent/US12010930B2

## CPC

- H10N 70/828: {Current flow limiting means within the switching material region, e.g. constrictions}
- H10N 70/026: {by physical vapor deposition, e.g. sputtering}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

## Claims

### Claim 1

A semiconductor structure comprising:
a phase change memory (PCM) element horizontally and electrically connecting a first contact and a second contact; and
a projection liner encapsulating the PCM element including a backside surface of the PCM element to position a portion of the projection liner directly between the PCM element and the second contact.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein spacers are formed adjacent the projection liner.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein spacers directly contact sidewalls of the projection liner.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein a hardmask layer is formed over the GST layer.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein sidewalls of the hardmask layer directly contact portions of the projection liner.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein conductive lines are formed between the PCM element and the first and second contacts.

### Claim 8

A semiconductor structure comprising:
a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact;
a metal layer disposed over each of the plurality of conductive lines;
a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines; and
a projection liner encapsulating the PCM element including both an upper surface and a backside surface of the PCM element, wherein a portion of the projection liner is directly between the PCM element and the metal layer.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein spacers are formed adjacent the projection liner.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein spacers directly contact sidewalls of the projection liner.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8, wherein the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein a hardmask layer is formed over the GST layer.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein sidewalls of the hardmask layer directly contact portions of the projection liner.

### Claim 14

A method comprising:
forming a phase change memory (PCM) element;
horizontally and electrically connecting the PCM element to a first contact and a second contact; and
encapsulating the PCM element with a projection liner including a backside surface of the PCM element to position a portion of the projection liner directly between the PCM element and the second contact.

### Claim 15 (depends on 14)

The method of claim 14, further comprising forming spacers adjacent the projection liner.

### Claim 16 (depends on 14)

The method of claim 14, wherein the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming a hardmask layer over the GST layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein sidewalls of the hardmask layer directly contact portions of the projection liner.

### Claim 19 (depends on 14)

The method of claim 14, wherein the PCM element defines a fin-type GST cell.

### Claim 20 (depends on 14)

The method of claim 14, wherein the PCM element is formed by physical vapor deposition (PVD).