# US 12,010,923 B2 · Semiconductor device and method for forming the same

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- Number: US 12,010,923 B2
- Document ID: US12010923B2
- Status: Granted
- Kind: B2
- Application number: 18/116,305
- Filed: 2023-03-02
- Published: 2023-06-29
- Granted: 2024-06-11
- Earliest claimed: 2020-11-16
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chih-Wei Kuo
- Web page: https://patentgrep.com/patent/US12010923B2

## CPC

- H10N 50/01: Manufacture or treatment
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a substrate having a logic region and a memory region, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer disposed on and directly contacting a top surface of the first interlayer dielectric layer. A portion of the top surface of the first interlayer dielectric layer on the memory region is lower than another portion of the top surface of the first interlayer dielectric layer on the logic region. A memory stack structure is disposed in the first interlayer dielectric layer on the memory region. A passivation layer covers a top surface and sidewalls of the memory stack structure and is in direct contact with the second interlayer dielectric layer. An upper contact structure penetrates through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure and directly contacts the memory stack structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a logic region and a memory region;
a first interlayer dielectric layer disposed on the substrate;
a second interlayer dielectric layer disposed on the first interlayer dielectric layer and directly contacts a top surface of the first interlayer dielectric layer, wherein a portion of the top surface of the first interlayer dielectric layer on the memory region is lower than another portion of the top surface of the first interlayer dielectric layer on the logic region;
a memory stack structure disposed in the first interlayer dielectric layer on the memory region;
a passivation layer covering a top surface and sidewalls of the memory stack structure, wherein the second interlayer dielectric layer directly contacts the passivation layer; and
an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure and directly contacting the memory stack structure.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a thickness of the first interlayer dielectric layer on the memory region is smaller than a thickness of the first interlayer dielectric layer on the logic region.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the thickness of the first interlayer dielectric layer on the logic region is different from the thickness of the first interlayer dielectric layer on the memory region by between 100 Å and 150 Å.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the first interlayer dielectric layer comprises a step portion near a boundary between the logic region and the memory region.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein a step-height of the step portion is between 100 Å and 150 Å.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a thickness of a portion of the passivation layer sandwiched between the top surface of the memory stack structure and the second interlayer dielectric layer is smaller than a thickness of another portion of the passivation layer on the sidewalls of the memory stack structure.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the thickness of the portion of the passivation layer sandwiched between the top surface of the memory stack structure and the second interlayer dielectric layer is between 60 Å and 100 Å, the thickness of the another portion of the passivation layer on the sidewalls of the memory stack structure is between 180 Å and 220 Å.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a first interconnecting structure disposed in the first interlayer dielectric layer on the logic region; and
a second interconnecting structure disposed in the second interlayer dielectric layer and contacting the first interconnecting structure, wherein a height of the memory stack structure is smaller than a height of the first interconnecting structure.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the second interlayer dielectric layer comprises:
an etching stop layer contacting the first interlayer dielectric layer and the passivation layer; and
a dielectric material layer on the etching stop layer.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the etching stop layer comprises nitride doped silicon carbide, the dielectric material layer comprises a low-k dielectric material, and the passivation layer comprises silicon nitride.