# US 12,010,871 B2 · Thin film transistor and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,010,871 B2 - Document ID: US12010871B2 - Status: Granted - Kind: B2 - Application number: 17/199,991 - Filed: 2021-03-12 - Published: 2021-07-01 - Granted: 2024-06-11 - Earliest claimed: 2018-09-25 - Assignees: Japan Display Inc. - Applicants: Japan Display Inc. - Inventors: Masashi Tsubuku; Tatsuya Toda - Web page: https://patentgrep.com/patent/US12010871B2 ## CPC - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - G09F 9/30: in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10K 59/1213: {the pixel elements being TFTs} - H10D 30/6736: {characterised by the shape of gate insulators} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT] - H10K 59/80516: {combined with auxiliary electrodes, e.g. ITO layer combined with metal lines} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G09F: DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A thin film transistor including: an active layer formed of an oxide semiconductor including at least indium and gallium; a gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; and a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side. ## Claims ### Claim 1 A thin film transistor comprising: an active layer formed of an oxide semiconductor including at least indium and gallium; a gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side; a second gate electrode provided on an opposite side of the active layer from the gate electrode; a third gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; and a fourth gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is greater than a total thickness of the third gate insulating layer and the fourth gate insulating layer. ### Claim 2 (depends on 1) The thin film transistor according to claim 1, wherein the first gate insulating layer is a silicon nitride layer, the second gate insulating layer is a silicon oxide layer, and the second gate insulating layer is thicker than the first gate insulating layer. ### Claim 3 (depends on 2) The thin film transistor according to claim 2, wherein a thickness of the first gate insulating layer is equal to or more than 30 nm and equal to or less than 400 nm, a thickness of the second gate insulating layer is equal to or more than 50 nm and equal to or less than 500 nm, and a total thickness of the first gate insulating layer and the second gate insulating layer is equal to or more than 400 nm. ### Claim 4 (depends on 2) The thin film transistor according to claim 2, wherein a difference in thickness between the first gate insulating layer and the second gate insulating layer is equal to or more than 50 nm. ### Claim 5 (depends on 2) The thin film transistor according to claim 2, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is equal to or less than 600 nm. ### Claim 6 (depends on 1) The thin film transistor according to claim 1, wherein the first gate insulating layer and the third gate insulating layer are silicon nitride layers, the second gate insulating layer and the fourth gate insulating layer are silicon oxide layers, the second gate insulating layer is thicker than the first gate insulating layer, and the fourth gate insulating layer is thicker than the third gate insulating layer. ### Claim 7 (depends on 6) The thin film transistor according to claim 6, wherein the first gate insulating layer and the third gate insulating layer each have a thickness of equal to or more than 30 nm and equal to or less than 400 nm, the second gate insulating layer and the fourth gate insulating layer each have a thickness of equal to or more than 50 nm and equal to or less than 500 nm, and a total thickness of the first gate insulating layer and the second gate insulating layer and a total thickness of the third gate insulating layer and the fourth gate insulating layer are each equal to or more than 400 nm. ### Claim 8 (depends on 6) The thin film transistor according to claim 6, wherein a difference in thickness between the first gate insulating layer and the second gate insulating layer is equal to or more than 50 nm, and a difference in thickness between the third gate insulating layer and the fourth gate insulating layer is equal to or more than 50 nm. ### Claim 9 (depends on 6) The thin film transistor according to claim 6, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is equal to or less than 600 nm, and a total thickness of the third gate insulating layer and the fourth gate insulating layer is equal to or less than 600 nm. ### Claim 10 A display device having a pixel, the pixel comprising: a thin film transistor; and a pixel electrode connected to the thin film transistor, wherein the thin film transistor includes: an active layer formed of an oxide semiconductor including at least indium and gallium; at least one gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side; a second gate electrode provided on an opposite side of the active layer from the gate electrode; a third gate insulating layer provided between the active layer and the gate electrode on the gate electrode side; and a fourth gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is greater than a total thickness of the third gate insulating layer and the fourth gate insulating layer. ### Claim 11 (depends on 10) The display device according to claim 10, wherein the first gate insulating layer is a silicon nitride layer, the second gate insulating layer is a silicon oxide layer, and the second gate insulating layer is thicker than the first gate insulating layer. ### Claim 12 (depends on 11) The display device according to claim 11, wherein a thickness of the first gate insulating layer is equal to or more than 30 nm and equal to or less than 400 nm, a thickness of the second gate insulating layer is equal to or more than 50 nm and equal to or less than 500 nm, and a total thickness of the first gate insulating layer and the second gate insulating layer is equal to or more than 400 nm. ### Claim 13 (depends on 11) The display device according to claim 11, wherein a difference in thickness between the first gate insulating layer and the second gate insulating layer is equal to or more than 50 nm. ### Claim 14 (depends on 11) The display device according to claim 11, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is equal to or less than 600 nm. ### Claim 15 (depends on 10) The display device according to claim 10, wherein the first gate insulating layer and the third gate insulating layer are silicon nitride layers, the second gate insulating layer and the fourth gate insulating layer are silicon oxide layers, the second gate insulating layer is thicker than the first gate insulating layer, and the fourth gate insulating layer is thicker than the third gate insulating layer. ### Claim 16 (depends on 15) The display device according to claim 15, wherein the first gate insulating layer and the third gate insulating layer each have a thickness of equal to or more than 30 nm and equal to or less than 400 nm, the second gate insulating layer and the fourth gate insulating layer each have a thickness of equal to or more than 50 nm and equal to or less than 500 nm, and a total thickness of the first gate insulating layer and the second gate insulating layer and a total thickness of the third gate insulating layer and the fourth gate insulating layer are each equal to or more than 400 nm. ### Claim 17 (depends on 15) The display device according to claim 15, wherein a difference in thickness between the first gate insulating layer and the second gate insulating layer is equal to or more than 50 nm, and a difference in thickness between the third gate insulating layer and the fourth gate insulating layer is equal to or more than 50 nm. ### Claim 18 (depends on 15) The display device according to claim 15, wherein a total thickness of the first gate insulating layer and the second gate insulating layer is equal to or less than 600 nm, and a total thickness of the third gate insulating layer and the fourth gate insulating layer is equal to or less than 600 nm.