# US 12,010,856 B2 · Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor

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- Number: US 12,010,856 B2
- Document ID: US12010856B2
- Status: Granted
- Kind: B2
- Application number: 17/874,284
- Filed: 2022-07-27
- Published: 2022-11-17
- Granted: 2024-06-11
- Earliest claimed: 2018-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Timothy Vasen; Mark Van Dal; Gerben Doornbos; Matthias Passlack
- Web page: https://patentgrep.com/patent/US12010856B2

## CPC

- H10K 10/484: {characterised by the channel regions}
- H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate}
- H10K 10/472: {the gate dielectric comprising only inorganic materials}
- H10K 10/481: {characterised by the gate conductors}
- H10K 10/482: {the IGFET comprising multiple separately-addressable gate electrodes}
- H10K 19/10: comprising field-effect transistors
- H10K 85/221: {Carbon nanotubes}
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

## Claims

### Claim 1

A semiconductor device having a gate-all-around field effect transistor, comprising:
carbon nanotubes (CNTs) disposed in a first layer and a second layer stacked over a substrate;
a gate structure formed around the CNTs in a channel region; and
a source/drain contact formed around the CNTs in a source/drain region, wherein:
two CNTs among the CNTs directly contact each other in a horizontal direction in the first layer, and the CNT are free from another CNT in a vertical direction, and
a total number of CNTs in the first layer is different from a total number of CNTs in the second layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure includes a gate dielectric layer wrapping around each of the CNTs, a work function adjustment layer formed on the gate dielectric layer and a body gate electrode layer formed on the work function adjustment layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the work function adjustment layer partially wraps around the CNTs with the gate dielectric layer.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the work function adjustment layer fully wraps around each of the CNTs with the gate dielectric layer.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein the gate dielectric layer includes one selected from the group consisting of HfO2 and Al2O3.

### Claim 6 (depends on 2)

The semiconductor device of claim 2, wherein the work function adjustment layer includes TiN.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising inner spacers formed between the gate structure and the source/drain contact.

### Claim 8

A semiconductor device having a gate-all-around field effect transistor (GAA FET), comprising:
a first GAA FET; and
a second GAA FET, wherein:
each of the first GAA FET and the second GAA FET includes:
carbon nanotubes (CNTs) disposed over a substrate;
a gate structure formed around the CNTs in a channel region and includes a gate electrode; and
a source/drain contact formed around the CNTs in a source/drain region, wherein:
the first GAA FET and the second GAA FET share the gate electrode, and
a total number of CNTs in the first GAA FET is different from a total number of CNTs in the second GAA FET.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the gate structure includes a gate dielectric layer wrapping around each of the CNTs, a work function adjustment layer formed on the gate dielectric layer and a body gate electrode layer formed on the work function adjustment layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the work function adjustment layer partially wraps around the CNTs with the gate dielectric layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the work function adjustment layer fully wraps around each of the CNTs with the gate dielectric layer.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the gate dielectric layer includes one selected from the group consisting of HfO2 and Al2O3.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the work function adjustment layer includes TiN.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, further comprising inner spacers formed between the gate structure and the source/drain contact.

### Claim 15

A semiconductor device having a gate-all-around field effect transistor, comprising:
carbon nanotubes (CNTs) disposed over a substrate;
a gate structure formed around the CNTs in a channel region; and
a source/drain contact formed around the CNTs in a source/drain region, wherein:
the CNTs are arranged in multiple layers,
the CNTs pass through the source/drain contact,
a pitch P between adjacent layers is 0.9×PA≤P≤1.1×PA, where PA is an average pitch of the multiple layers, and
wherein a total number of CNTs in at least one layer is different from a total number of CNTs in another layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate structure includes a gate dielectric layer wrapping around each of the CNTs, a work function adjustment layer formed on the gate dielectric layer and a body gate electrode layer formed on the work function adjustment layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the work function adjustment layer partially wraps around the CNTs with the gate dielectric layer.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the work function adjustment layer fully wraps around each of the CNTs with the gate dielectric layer.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the gate dielectric layer includes one selected from the group consisting of HfO2 and Al2O3.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the work function adjustment layer includes TiN.