# US 12,010,850 B2 · Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,010,850 B2 - Document ID: US12010850B2 - Status: Granted - Kind: B2 - Application number: 18/218,762 - Filed: 2023-07-06 - Published: 2024-01-04 - Granted: 2024-06-11 - Earliest claimed: 2019-12-02 - Applicants: Lodestar Licensing Group LLC - Inventors: John D. Hopkins; Justin B. Dorhout; Nirup Bandaru; Damir Fazil; Nancy M. Lomeli; Jivaan Kishore Jhothiraman; Purnima Narayanan - Web page: https://patentgrep.com/patent/US12010850B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - G11C 16/08: Address circuits; Decoders; Word-line control circuits - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies. ## Claims ### Claim 1 An apparatus, comprising: a first deck, wherein the first deck includes: first memory cells arranged in first tiers disposed one atop another; and first inner lateral edges; a second deck over the first deck, wherein the second deck includes: second memory cells arranged in second tiers disposed one atop another; and second inner lateral edges; an inter-deck structure between the first deck and the second deck, wherein the inter-deck structure includes: an etch-stop material against the first deck; and an inter-deck material having third inner lateral edges, wherein the first inner lateral edges, the second inner lateral edges, and the third inner lateral edges are substantially straight relative to each other; and a pillar passing through the first deck, the second deck, and the inter-deck structure, wherein the pillar includes a channel material, a tunneling material, a charge-storage material, a charge-blocking material, and a dielectric barrier material. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the etch-stop material has fourth inner lateral edges that are substantially straight relative to the first inner lateral edges, the second inner lateral edges, and the third inner lateral edges. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the pillar has substantially straight vertical sidewalls as it passes through the inter-deck structure. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the pillar has substantially straight vertical sidewalls as it passes through the first deck. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the first memory cells include first control gate regions comprising a first conductive material vertically between horizontally-extending portions of a second conductive material; and the second memory cells include second control gate regions comprising a third conductive material and a fourth conductive material along an outer surface of the third conductive material. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein: the first conductive material and the second conductive material are different conductive materials; and the third conductive material and the fourth conductive material are different conductive materials. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein: the first control gate regions have first terminal edges comprising both the first conductive material and the second conductive material; and the second control gate regions have second terminal edges comprising only the fourth conductive material. ### Claim 8 An apparatus, comprising: a first deck, wherein the first deck includes: first memory cells arranged in first tiers disposed one atop another; and first inner lateral edges; a second deck over the first deck, wherein the second deck includes: second memory cells arranged in second tiers disposed one atop another; and second inner lateral edges; an inter-deck structure between the first deck and the second deck, wherein the inter-deck structure includes: an inter-deck material having third inner lateral edges; and an etch-stop material against the first deck and having fourth inner lateral edges which are laterally offset relative to the first inner lateral edges and the second inner lateral edges; and a pillar passing through the first deck, the second deck, and the inter-deck structure, wherein the pillar includes a channel material, a tunneling material, a charge-storage material, a charge-blocking material, and a dielectric barrier material. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the pillar has substantially straight vertical sidewalls as it passes through the first deck and the second deck. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the first inner lateral edges of the first deck and the second inner lateral edges of the second deck are along the vertical sidewalls of the pillar. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein the third inner lateral edges are laterally offset relative to the first inner lateral edges and the second inner lateral edges. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein the third lateral edges of the inter-deck material interface with the dielectric barrier material of the pillar. ### Claim 13 (depends on 8) The apparatus of claim 8, wherein the dielectric barrier material laterally surrounds the channel material, the tunneling material, the charge-storage material, and the charge-blocking material. ### Claim 14 An apparatus, comprising: a first deck, wherein the first deck includes a first stack of alternating first and second materials; a second deck over the first deck, wherein the second deck includes a second stack of alternating third and fourth materials; an inter-deck structure between the first deck and the second deck, wherein the inter-deck structure includes: an etch-stop material against the first deck; and an inter-deck material, wherein the inter-deck material is softer than the third and fourth materials of the second deck; and a pillar passing through the first deck, the second deck, and the inter-deck structure, wherein the pillar includes a channel material, a tunneling material, a charge-storage material, a charge-blocking material, and a dielectric barrier material. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the inter-deck material has a lower density than the third and fourth materials of the second deck. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the inter-deck material is a silicon dioxide material. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the fourth material of the second deck is a silicon dioxide material having a lower density than the silicon dioxide material of the inter-deck material. ### Claim 18 (depends on 14) The apparatus of claim 14, wherein one or more dopants are provided within the inter-deck material. ### Claim 19 (depends on 14) The apparatus of claim 14, wherein the etch-stop material is harder than the inter-deck material. ### Claim 20 (depends on 14) The apparatus of claim 14, wherein the etch-stop material is an aluminum oxide material.