# US 12,010,844 B2 · Semiconductor device and method of manufacturing the semiconductor device

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- Number: US 12,010,844 B2
- Document ID: US12010844B2
- Status: Granted
- Kind: B2
- Application number: 17/216,093
- Filed: 2021-03-29
- Published: 2022-03-31
- Granted: 2024-06-11
- Earliest claimed: 2020-09-29
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Hun Lee; Mi Seong Park; Jung Shik Jang; Jung Dal Choi; In Su Park
- Web page: https://patentgrep.com/patent/US12010844B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10B 43/10: characterised by the top-view layout
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 64/037: {comprising charge-trapping insulators}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.

## Claims

### Claim 1

A semiconductor device, comprising:
a stacked body including conductive patterns and insulating patterns that are alternately stacked;
a filling layer configured to pass through the stacked body;
a first channel layer configured to pass through the stacked body and coupled to the filling layer;
a second channel layer configured to pass through the stacked body and coupled to the filling layer;
a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer;
a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer; and
a memory layer configured to surround the filling layer, the first and second channel layers, and the first and second interposed layers, wherein the memory layer includes a first blocking layer, a first data storage layer, and a first tunnel insulating layer adjacent to the first channel layer, and a second blocking layer, a second data storage layer, and a second tunnel insulating layer adjacent to the second channel layer,
the first blocking layer and the second blocking layer are coupled to each other, the first data storage layer and the second data storage layer are coupled to each other, and the first tunnel insulating layer and the second tunnel insulating layer are coupled to each other, and
an entirety of an inside wall of the first channel layer is in contact with the first interposed layer and an entirety of an inside wall of the second channel layer is in contact with the second interposed layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein:
the first interposed layer is surrounded by the first channel layer and the filling layer, and
the second interposed layer is surrounded by the second channel layer and the filling layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein:
each of the first channel layer and the second channel layer has a shape of substantially a circular arc.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein:
the first channel layer includes a first junction surface and a second junction surface that both contact with the filling layer, and
the first interposed layer is disposed between the first junction surface and the second junction surface.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein:
the filling layer comprises a first protrusion and a second protrusion that both contact with the first channel layer, and
the first interposed layer is disposed between the first protrusion and the second protrusion.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the filling layer further comprises a filling part disposed between the first protrusion and the second protrusion.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein:
a width of the filling part is smaller in a direction closer to the first channel layer.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, wherein the first interposed layer comprises a first portion disposed between the first protrusion and the filling part and a second portion disposed between the second protrusion and the filling part.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein:
a width of the first portion of the first interposed layer is greater in a direction closer to the first channel layer, and
a width of the second portion of the first interposed layer is greater in a direction closer to the first channel layer.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein a maximum length of the first interposed layer is greater than a maximum length of the second interposed layer.

### Claim 11

A semiconductor device, comprising:
a stacked body including conductive patterns and insulating patterns that are alternately stacked;
a filling layer configured to pass through the stacked body;
a first channel layer configured to pass through the stacked body and coupled to the filling layer;
a second channel layer configured to pass through the stacked body and coupled to the filling layer;
a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer;
a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer; and
a memory layer configured to surround the filling layer, the first channel layer, and the second channel layer,
wherein the filling layer comprises a first protrusion and a second protrusion that both contact with the first channel layer,
wherein the first protrusion includes a first outside wall in contact with the memory layer and a first junction surface in contact with the first channel layer,
wherein the second protrusion includes a second outside wall in contact with the memory layer and a second junction surface in contact with the first channel layer,
wherein the first outside wall and the second outside wall are substantially parallel to each other, and
wherein the memory layer includes a first blocking layer, a first data storage layer, and a first tunnel insulating layer adjacent to the first channel layer, and a second blocking layer, a second data storage layer, and a second tunnel insulating layer adjacent to the second channel layer,
the first blocking layer and the second blocking layer are coupled to each other, the first data storage layer and the second data storage layer are coupled to each other, and the first tunnel insulating layer and the second tunnel insulating layer are coupled to each other, and
an entirety of an inside wall of the first channel layer is in contact with the first interposed layer and an entirety of an inside wall of the second channel layer is in contact with the second interposed layer.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the first outside wall and the first junction surface intersect each other.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the first outside wall and the first junction surface are substantially orthogonal to each other.

### Claim 14 (depends on 11)

The semiconductor device according to claim 11, wherein the first interposed layer is disposed between the first junction surface and the second junction surface.