# US 12,010,839 B2 · Semiconductor device including contact structure and method of manufacturing semiconductor device

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- Number: US 12,010,839 B2
- Document ID: US12010839B2
- Status: Granted
- Kind: B2
- Application number: 17/970,360
- Filed: 2022-10-20
- Published: 2023-02-09
- Granted: 2024-06-11
- Earliest claimed: 2019-07-24
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Nam Jae Lee
- Web page: https://patentgrep.com/patent/US12010839B2

## CPC

- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10W 20/43: Layouts of interconnections
- H10B 20/60: {Peripheral circuit regions}
- H10B 43/40: characterised by the peripheral circuit region
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/10: characterised by the top-view layout
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device may include a plurality of first contact structures, plug-shaped second contact structures configured to be connected to a first number of the plurality of first contact structures, respectively, a slit-shaped second contact structure configured to be connected to a second number of the plurality of first contact structures, adjacent in a first direction, and a third contact structure configured to be connected to sidewalls of the plug-shaped second contact structures, adjacent in the first direction.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a transistor over a substrate;
forming a plurality of first contact structures;
forming plug-shaped second contact structures electrically connected to a first number of the plurality of first contact structures, respectively;
forming a slit-shaped second contact structure to extend in a horizontal direction and directly connected to upper surfaces of first contact structures adjacent in the first direction, among the plurality of first contact structures, to electrically connect the first contact structures adjacent in the first direction to each other; and
forming a third contact structure to be electrically connected to sidewalls of the plug-shaped second contact structures, adjacent in the first direction,
wherein the plurality of first contact structures are connected to the transistor, and
wherein the transistor includes a source region and a drain region, the source region is connected to the slit-shaped second contact structure through one of a second number of the plurality of first contact structures, and the drain region is connected to the third contact structure through one of a first number of the plurality of first contact structures and one of the plug-shaped second contact structures.

### Claim 2 (depends on 1)

The method of claim 1,
wherein the transistor belongs to a page buffer.

### Claim 3 (depends on 1)

The method of claim 1,
wherein the slit-shaped second contact structure is formed when forming the plug-shaped second contact structures.

### Claim 4 (depends on 1)

The method of claim 1,
wherein the third contact structure is misaligned with the plurality of first contact structures, and the misaligned third contact structure and the plurality of first contact structures are connected to each other through the plug-shaped second contact structures.

### Claim 5 (depends on 1)

The method of claim 1,
wherein the slit-shaped second contact structure and the third contact structure are adjacent to each other in a second direction crossing the first direction.

### Claim 6

A method of manufacturing a semiconductor device, the method comprising:
forming a first interlayer insulating film;
forming a plurality of first contact structures to pass through the first interlayer insulating film;
forming an etch stop film on the first interlayer insulating film;
forming a second interlayer insulating film on the etch stop film;
forming plug-shaped second contact structures to pass through the etch stop film and the second interlayer insulating film and electrically connected to a first number of the plurality of first contact structures, respectively;
forming a slit-shaped second contact structure to pass through the etch stop film and the second interlayer insulating film, to be electrically connected to second number of the plurality of first contact structures, and to extend in a first direction; and
forming a third contact structure to pass through the second interlayer insulating film, to be electrically connected to sidewalls of the plug-shaped second contact structures, and to extend in the first direction.

### Claim 7 (depends on 6)

The method of claim 6,
wherein the slit-shaped second contact structure is formed when forming the plug-shaped second contact structures.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
forming a cell array including a source line, bit lines, and memory strings connected between the source line and the bit lines; and
forming a page buffer including a transistor,
wherein the bit lines and the page buffer are connected to each other by an interconnect structure including the plurality of first contact structures, the plug-shaped second contact structures, the slit-shaped second contact structure, and the third contact structure.

### Claim 9 (depends on 8)

The method of claim 8,
wherein the transistor includes a source region and a drain region, and the source region or the drain region is connected to the bit line through one of the second number of the plurality of first contact structures and the slit-shaped second contact structure.

### Claim 10 (depends on 8)

The method of claim 8,
wherein the transistor includes a source region and a drain region, and the source region or the drain region is connected to the bit line through one of the first number of the plurality of first contact structures, one of the plug-shaped second contact structures, and the third contact structure.

### Claim 11 (depends on 6)

The method of claim 6, wherein forming the plurality of first contact structures comprises:
etching the first interlayer insulating film to form first openings; and
forming the plurality of first contact structures in the first openings.

### Claim 12 (depends on 6)

The method of claim 6, wherein forming the plug-shaped second contact structures comprises:
etching the second interlayer insulating film to expose the etch stop film;
etching the exposed etch stop film to form second openings exposing the plurality of first contact structures, respectively; and
forming the plug-shaped second contact structures in the second openings, respectively.

### Claim 13 (depends on 6)

The method of claim 6, wherein forming the slit-shaped second contact structure comprises:
etching the second interlayer insulating film to expose the etch stop film;
etching the exposed etch stop film to form a third opening exposing the plug-shaped second contact structures adjacent in the first direction; and
forming the slit-shaped second contact structure in the third opening.

### Claim 14 (depends on 6)

The method of claim 6, wherein forming the third contact structure comprises:
etching the second interlayer insulating film to form a fourth opening exposing sidewalls of the plug-shaped second contact structures adjacent in the first direction; and
forming a third contact structure in the fourth opening.

### Claim 15 (depends on 6)

The method of claim 6,
wherein the slit-shaped second contact structure and the third contact structure are adjacent to each other in a second direction crossing the first direction.