# US 12,010,838 B2 · Staircase structure for memory device

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- Number: US 12,010,838 B2
- Document ID: US12010838B2
- Status: Granted
- Kind: B2
- Application number: 17/447,456
- Filed: 2021-09-13
- Published: 2023-03-16
- Granted: 2024-06-11
- Earliest claimed: 2017-08-28
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Zhenyu Lu; Jun Chen; Xiaowang Dai; Jifeng Zhu; Qian Tao; Yu Ru Huang; Si Ping Hu; Lan Yao; Li Hong Xiao; A Man Zheng; Kun Bao; Haohao Yang
- Web page: https://patentgrep.com/patent/US12010838B2

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10P 50/73: {using masks for insulating materials}
- H10P 76/204: {of organic photoresist masks}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4432: {the principal metal being a noble metal, e.g. gold}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

## Claims

### Claim 1

A staircase structure of a memory device, comprising:
a first material layer and a second material layer, wherein the first material layer is disposed over a first portion of the second material layer; and
a landing pad disposed over a second portion of the second material layer, wherein the landing pad comprises a first side surface and a second side surface, and wherein the first side surface is in contact with the first material layer and the second side surface is laterally displaced from a side surface of the second portion of the second material layer.

### Claim 2 (depends on 1)

The staircase structure of claim 1, further comprising a dielectric layer in contact with a bottom surface of the landing pad, the second side surface of the landing pad, and the side surface of the second portion of the second material layer.

### Claim 3 (depends on 1)

The staircase structure of claim 1, wherein a lateral distance between the second side surface and the side surface of the second portion of the second material layer is between 10 nm and 300 nm.

### Claim 4 (depends on 1)

The staircase structure of claim 1, wherein the landing pad comprises a conductive material.

### Claim 5 (depends on 4)

The staircase structure of claim 4, wherein the conductive material comprises tungsten, silicide, nickel, titanium, platinum, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

### Claim 6 (depends on 1)

The staircase structure of claim 1, wherein the second material layer is disposed over a first portion of another first material layer, and wherein a side surface of a second portion of the another first material layer is laterally displaced from the second side surface of the landing pad.

### Claim 7 (depends on 1)

The staircase structure of claim 1, wherein the second material layer comprises a first conductive material and the landing pad comprises a second conductive material substantially the same as the first conductive material.

### Claim 8

A memory device, comprising:
a memory string disposed over a substrate; and
a staircase structure disposed adjacent to the memory string, wherein the staircase structure comprises:
a conductive layer comprising first and second portions;
an insulating layer disposed over the first portion of the conductive layer, wherein the insulating layer comprises a first thickness; and
a landing pad disposed on the second portion of the conductive layer and in contact with a side surface of the insulating layer, wherein the landing pad comprises a second thickness greater than the first thickness.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the conductive layer is disposed over a first portion of another insulating layer, wherein a second portion of the another insulating layer is laterally displaced from the conductive layer.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the conductive layer comprises a first conductive material and the landing pad comprises a second conductive material substantially the same as the first conductive material.

### Claim 11 (depends on 10)

The memory device of claim 10, further comprising a dielectric layer in contact with a bottom surface of the landing pad, a side surface of the landing pad, and a side surface of the second portion of the conductive layer.

### Claim 12

A memory device, comprising:
a first material layer and a second material layer, wherein the first material layer is disposed over a first portion of the second material layer; and
a landing pad disposed over a second portion of the second material layer, wherein the landing pad comprises a first side surface and a second side surface, and wherein the first side surface is in contact with the first material layer and the second side surface is laterally displaced from a side surface of the second portion of the second material layer.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the first side surface comprises a curved side surface.

### Claim 14 (depends on 13)

The memory device of claim 13, further comprising another second material layer disposed on the first material layer, wherein a first lateral distance between the first side surface and a side surface of the another second material layer is smaller than a second lateral distance between the second side surface and the side surface of the another second material layer.

### Claim 15 (depends on 13)

The memory device of claim 13, wherein the second side surface is laterally displaced from the first side surface, and wherein a first lateral distance between the first side surface and the first portion of the second material layer is smaller than a second lateral distance between the second side surface and the first portion of the second material layer.

### Claim 16 (depends on 12)

The memory device of claim 12, wherein the second material layer comprises tungsten, and titanium nitride.

### Claim 17 (depends on 12)

The memory device of claim 12, wherein the second material layer comprises a first conductive material and the landing pad comprises a second conductive material substantially the same as the first conductive material.

### Claim 18 (depends on 12)

The memory device of claim 12, wherein a lateral distance between the second side surface and the side surface of the second portion of the second material layer is between 10 nm and 300 nm.

### Claim 19 (depends on 12)

The memory device of claim 12, further comprising:
a dielectric layer disposed over the first material layer and the landing pad, wherein the first material layer comprises a first dielectric material and the dielectric layer comprises a second dielectric material, wherein the first dielectric material is substantially the same as the second dielectric material, and wherein the first dielectric material comprises silicon oxide.

### Claim 20 (depends on 12)

The memory device of claim 12, wherein the second material layer is disposed over a first portion of another first material layer, and wherein a side surface of a second portion of the another first material layer is laterally displaced from the second side surface of the landing pad.