# US 12,010,837 B2 · Semiconductor memory device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,010,837 B2 - Document ID: US12010837B2 - Status: Granted - Kind: B2 - Application number: 17/886,164 - Filed: 2022-08-11 - Published: 2022-12-01 - Granted: 2024-06-11 - Earliest claimed: 2019-08-28 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Yusuke Shima - Web page: https://patentgrep.com/patent/US12010837B2 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 62/40: Crystalline structures - H10P 50/242: {of Group IV materials} - H10P 72/0422: {for wet etching} - H10P 95/062: {involving a dielectric removal step} - H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]} - H10B 43/10: characterised by the top-view layout - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region. ## Claims ### Claim 1 A semiconductor memory device comprising: a substrate including a first region over which a plurality of memory cells for storing data are disposed and a second region arranged on an outer side of the first region in a first direction; a stacked structure including a plurality of conductive layers separated from each other in the stacked structure in a second direction perpendicular to the first direction above the first region of the substrate and including a plurality of first layers separated from each other in the stacked structure in the second direction above the second region of the substrate; and a plurality of columnar structures that extend in the second direction and are opposed to the conductive layers above the first region of the substrate, the columnar structures forming the memory cells at intersections with at least some of the plurality of conductive layers, wherein the conductive layers include a plurality of first conductive layers and a plurality of second conductive layers arranged in the second direction, and the first layers include a plurality of first films disposed in same layers as the first conductive layers and a plurality of second films disposed in same layers as the second conductive layers, the first and second films being arranged in the second direction, the first films being different in material from the first conductive layers, the second films being different in material from the second conductive layers, the first conductive layers of the conductive layers and the first films of the first layers in the stacked structure are coupled with each other in the first direction, and the second conductive layers of the conductive layers and the second films of the first layers in the stacked structure are coupled with each other in the first direction, and respective coupling portions of the first films with the first conductive layers are farther from the first region in the first direction than respective coupling portions of the second films with the second conductive layers. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the stacked structure further includes a plurality of insulating layers, the insulating layers being different in material from the first films, the insulating layers being different in material from the second films, the conductive layers and the insulating layers being alternately stacked in the second direction above the first region of the substrate, and the first layers and the insulating layers being alternately stacked in the second direction above the second region of the substrate. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein the substrate further includes a third region between the first region and the second region in the first direction, and the first conductive layers and the second films are separated from each other in the stacked structure in the second direction above the third region of the substrate. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the second conductive layers and the first films are not disposed above the third region of the substrate. ### Claim 5 (depends on 3) The semiconductor memory device according to claim 3, wherein the insulating layers are provided above the first, second, and third regions of the substrate. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein each of upper surfaces and lower surfaces of the second films is in contact with a corresponding one of the insulating layers above the third region of the substrate. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein the second films include silicon nitride. ### Claim 8 (depends on 6) The semiconductor memory device according to claim 6, wherein the insulating layers include silicon oxide. ### Claim 9 (depends on 3) The semiconductor memory device according to claim 3, wherein at least one second film is disposed above the first conductive layers and at least another second film is disposed below the first conductive layers above the third region of the substrate. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, wherein an etching rate of the first films with respect to phosphoric acid is different from an etching rate of the second films with respect to phosphoric acid. ### Claim 11 A semiconductor memory device comprising: a substrate including a first region and a second region arranged in a first direction; a stacked structure including a plurality of conductive layers separated from each other in the stacked structure in a second direction perpendicular to the first direction above the first region of the substrate and including a plurality of first layers separated from each other in the stacked structure in the second direction above the second region of the substrate; a semiconductor layer that extends in the second direction and is opposed to the conductive layers; and a gate insulating layer disposed between the conductive layers and the semiconductor layer, wherein the conductive layers include a plurality of first conductive layers and a plurality of second conductive layers arranged in the second direction, and the first layers include a plurality of first films disposed in same layers as the first conductive layers and a plurality of second films disposed in same layers as the second conductive layers, the first and second films being arranged in the second direction, the first films being different in material from the first conductive layers, the second films being different in material from the second conductive layers, the first conductive layers of the conductive layers and the first films of the first layers in the stacked structure are coupled with each other in the first direction, and the second conductive layers of the conductive layers and the second films of the first layers in the stacked structure are coupled with each other in the first direction, and respective coupling portions of the first films with the first conductive layers are approximately aligned in the second direction and substantially away from respective coupling portions of the second films with the second conductive layers in the first direction. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, wherein the stacked structure further includes a plurality of first insulating layers, the first insulating layers being different in material from the first films, the first insulating layers being different in material from the second films, the conductive layers and the first insulating layers being alternately stacked in the second direction above the first region of the substrate, and the first layers and the first insulating layers being alternately stacked in the second direction above the second region of the substrate. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, wherein the substrate further includes a third region between the first region and the second region in the first direction, and the first conductive layers and the second films are separated from each other in the stacked structure in the second direction above the third region of the substrate. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, wherein the second conductive layers and the first films are not disposed above the third region of the substrate. ### Claim 15 (depends on 13) The semiconductor memory device according to claim 13, wherein the first insulating layers are provided above the first, second, and third regions of the substrate. ### Claim 16 (depends on 15) The semiconductor memory device according to claim 15, wherein each of upper surfaces and lower surfaces of the second films is in contact with a corresponding one of the first insulating layers above the third region of the substrate. ### Claim 17 (depends on 16) The semiconductor memory device according to claim 16, wherein the second films include silicon nitride. ### Claim 18 (depends on 16) The semiconductor memory device according to claim 16, wherein the first insulating layers include silicon oxide. ### Claim 19 (depends on 13) The semiconductor memory device according to claim 13, wherein at least one second film is disposed above the first conductive layers and at least another second film is disposed below the first conductive layers above the third region of the substrate. ### Claim 20 (depends on 11) The semiconductor memory device according to claim 11, wherein an etching rate of the first films with respect to phosphoric acid is different from an etching rate of the second films with respect to phosphoric acid.