# US 12,010,836 B2 · Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,010,836 B2 - Document ID: US12010836B2 - Status: Granted - Kind: B2 - Application number: 17/319,246 - Filed: 2021-05-13 - Published: 2021-09-30 - Granted: 2024-06-11 - Earliest claimed: 2019-07-10 - Applicants: Micron Technology, Inc. - Inventors: David Daycock; Prakash Rau Mokhna Rau - Web page: https://patentgrep.com/patent/US12010836B2 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/10: characterised by the top-view layout - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - H10D 64/037: {comprising charge-trapping insulators} - H10P 50/264: {by chemical means} - H10P 50/283: {by chemical means} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed. ## Claims ### Claim 1 A memory array comprising: a vertical stack comprising alternating insulative tiers and conductive tiers, the conductive tiers comprising gate regions of individual memory cells, the gate regions individually comprising part of a conductive line in individual of the conductive tiers; operative channel-material strings extending through the insulative tiers and the conductive tiers within a memory plane; the individual memory cells comprising a memory structure laterally between individual of the gate regions and channel material of the operative channel-material strings; and the vertical stack comprising a through-array-via (TAV) region that is outside of the memory plane and comprising multiple operative TAVs and multiple dummy TAVs, the dummy TAVs being devoid of any conductive material and being devoid of any channel material. ### Claim 2 (depends on 1) The memory array of claim 1 wherein the operative channel-material strings and the dummy TAVs individually have the same horizontal shape relative one another. ### Claim 3 (depends on 1) The memory array of claim 1 wherein the operative channel-material strings and the dummy TAVs individually have the same size and shape relative one another. ### Claim 4 (depends on 1) The memory array of claim 1 wherein the operative channel-material strings and the dummy TAVs have the same pitch relative one another. ### Claim 5 (depends on 4) The memory array of claim 4 wherein the operative channel-material strings and the dummy TAVs individually have the same size and shape relative one another. ### Claim 6 (depends on 1) The memory array of claim 1 wherein the operative channel-material strings and the dummy TAVs individually are horizontally smaller than the operative TAVs. ### Claim 7 (depends on 1) The memory array of claim 1 comprising CMOS-under-array circuitry. ### Claim 8 (depends on 1) The memory array of claim 1 comprising NAND. ### Claim 9 A memory array comprising: a vertical stack comprising alternating insulative tiers and conductive tiers, the conductive tiers comprising gate regions of individual memory cells, the gate regions individually comprising part of a conductive line in individual of the conductive tiers; operative channel-material strings extending through the insulative tiers and the conductive tiers within a memory plane; the individual memory cells within the memory plane comprising a memory structure laterally between individual of the gate regions and channel material of the operative channel-material strings; and the vertical stack comprising a through-array-via (TAV) region comprising multiple operative TAVs and multiple dummy TAVs, the TAV region being one outside of the memory plane at an edge of the memory plane, the dummy TAVs being devoid of any conductive material and being devoid of any channel material. ### Claim 10 (depends on 9) The memory array of claim 9 wherein the operative channel-material strings and the dummy TAVs have the same pitch relative to one another. ### Claim 11 (depends on 9) The memory array of claim 9 wherein the the operative channel-material strings and the dummy TAVs individually have the same size and shape relative to one another. ### Claim 12 (depends on 9) The memory array of claim 9 wherein the operative channel-material strings and the dummy TAVs individually are horizontally smaller than the operative TAVs. ### Claim 13 (depends on 9) The memory array of claim 9 wherein the dummy TAVs comprise insulator material. ### Claim 14 (depends on 13) The memory array of claim 13 wherein the insulator material comprises solid material and gaseous material. ### Claim 15 (depends on 14) The memory array of claim 14 wherein the insulator material comprises one and only one void space and in which the gaseous material is received. ### Claim 16 (depends on 9) The memory array of claim 9 wherein the dummy TAVs consist essentially of solid insulator material. ### Claim 17 (depends on 9) The memory array of claim 9 wherein the dummy TAVs consist of silicon nitride. ### Claim 18 A memory array comprising: a vertical stack comprising alternating insulative tiers and conductive tiers, the conductive tiers comprising gate regions of individual memory cells, the gate regions individually comprising part of a conductive line in individual of the conductive tiers; operative channel-material strings extending through the insulative tiers and the conductive tiers within a memory plane; the individual memory cells within the memory plane comprising a memory structure laterally between individual of the gate regions and channel material of the operative channel-material strings; an operative stair-step structure outside of the memory plane and comprising the insulative tiers and the conductive tiers; and a landing region adjacent steps of the operative stair-step structure, the landing region comprising a through-array-via (TAV) region that is outside the memory plane and operative TAVs that extend through the insulative tiers and the conductive tiers, the landing region further comprising dummy TAVs extending through the insulative tiers and the conductive tiers, the dummy TAVs being devoid of any conductive material and being devoid of any channel material.