# US 12,010,835 B2 · Three-dimensional memory device with a conductive drain-select-level spacer and methods for forming the same

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- Number: US 12,010,835 B2
- Document ID: US12010835B2
- Status: Granted
- Kind: B2
- Application number: 17/241,321
- Filed: 2021-04-27
- Published: 2022-10-27
- Granted: 2024-06-11
- Earliest claimed: 2021-04-27
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Zhixin Cui; Satoshi Shimizu
- Web page: https://patentgrep.com/patent/US12010835B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 8/14: Word line organisation; Word line lay-out
- H10B 41/10: characterised by the top-view layout
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the alternating stack in a memory array region, and an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer to a second drain-select-level electrically conductive layer.

## Claims

### Claim 1

A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers, wherein the electrically conductive layers comprise word-line-level electrically conductive layers and drain-select-level electrically conductive layers located above the word-line-level electrically conductive layers;
a first backside trench fill structure extending along a first horizontal direction and comprising a first dielectric surface that contacts first sidewalls of each layer within the alternating stack;
a second backside trench fill structure extending along the first horizontal direction, separated from the first backside trench fill structure along a second horizontal direction perpendicular to the first horizontal direction, and comprising a second dielectric surface that contacts second sidewalls of each layer within the alternating stack;
a contact-level dielectric layer overlying the alternating stack;
drain-select-level isolation structures extending through the contact-level dielectric layer and the drain-select-level electrically conductive layers but not through the word-line-level electrically conductive layers of the alternating stack, wherein the drain-select-level isolation structures extend in the first horizontal direction and are spaced apart along the second horizontal direction;
memory opening fill structures vertically extending through the alternating stack in a memory array region in which each layer within the alternating stack is present, wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a memory film, wherein an entirety of the memory opening fill structures underlies a bottom surface of the contact-level dielectric layer;
an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers to a second drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers, wherein the electrically conductive spacer extends along the second horizontal direction and contacts ends of the first and the second drain-select-level electrically conductive layers along the second horizontal direction; and
an additional electrically conductive spacer extending vertically and electrically connecting a third drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers to a fourth drain-select-level electrically conductive layer of the drain-select-level electrically conductive layers.

### Claim 2 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the additional electrically conductive spacer extends along the second horizontal direction and contacts ends of the third and the fourth drain-select-level electrically conductive layers along the second horizontal direction;
the additional electrically conductive spacer is vertically offset from the electrically conductive spacer; and
the additional electrically conductive spacer is laterally offset from the electrically conductive spacer along the first horizontal direction.