# US 12,010,834 B2 · Three-dimensional memory devices with stabilization structures between memory blocks and methods for forming the same

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- Number: US 12,010,834 B2
- Document ID: US12010834B2
- Status: Granted
- Kind: B2
- Application number: 17/084,297
- Filed: 2020-10-29
- Published: 2022-02-17
- Granted: 2024-06-11
- Earliest claimed: 2020-08-17
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Kun Zhang
- Web page: https://patentgrep.com/patent/US12010834B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/941: {Dispositions of bond pads}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/792: {between multiple chips}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a plurality of memory blocks in a plan view and at least one stabilization structure extending laterally to separate adjacent ones of the memory blocks in the plan view. Each of the memory blocks includes a memory stack including vertically interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending vertically through the memory stack. The stabilization structure includes a dielectric stack including vertically interleaved second dielectric layers and the first dielectric layers.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a plurality of memory blocks arranged in a bit line direction in a plan view, wherein each of the memory blocks comprises:
a memory stack comprising vertically interleaved conductive layers and first dielectric layers on a semiconductor stack including a first semiconductor layer and a second semiconductor layer; and
a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer into the second semiconductor layer; and
at least one stabilization structure extending laterally in a word line direction to separate adjacent ones of the memory blocks in the plan view, wherein the stabilization structure comprises a dielectric stack comprising vertically interleaved second dielectric layers and the first dielectric layers, and a residual stop layer coplanar with the first semiconductor layer and in contact with the second semiconductor layer.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, wherein the bit line direction is perpendicular to the word line direction in the plan view.

### Claim 3 (depends on 1)

The 3D memory device of claim 1, wherein each of the first dielectric layers extends laterally across the stabilization structure and the memory stacks.

### Claim 4 (depends on 1)

The 3D memory device of claim 1, wherein the first dielectric layers comprise silicon oxide, and the second dielectric layers comprise silicon nitride.

### Claim 5 (depends on 1)

The 3D memory device of claim 1, wherein the stabilization structure further comprises a residual sacrificial layer coplanar with the first semiconductor layer.

### Claim 6 (depends on 5)

The 3D memory device of claim 5, wherein the residual sacrificial layer comprises polysilicon or silicon nitride, and the residual stop layer comprises silicon oxide.

### Claim 7 (depends on 1)

The 3D memory device of claim 1, wherein each of the memory blocks further comprises at least one slit structure having an “H” cut, the slit structure extending vertically through the memory stack and extending laterally to form a plurality memory fingers in the respective memory block in the plan view.

### Claim 8 (depends on 1)

The 3D memory device of claim 1, further comprising a source contact in contact with the second semiconductor layer without in contact with the first semiconductor layer.

### Claim 9

A three-dimensional (3D) memory device, comprising:
a plurality of memory blocks arranged in a bit line direction in a plan view, each of the memory blocks comprising a plurality of memory fingers arranged in the bit line direction and at least one slit structure having an “H” cut each between adjacent ones of the memory fingers in the bit line direction, each of the memory fingers comprising an array of channel structures;
a semiconductor stack including a first semiconductor layer and a second semiconductor layer, wherein the channel structures each extending vertically through the first semiconductor layer into the second semiconductor layer; and
at least one stabilization structure each extending laterally in a word line direction between adjacent ones of the memory blocks in the bit line direction, wherein the stabilization structure comprises a dielectric stack comprising vertically interleaved first dielectric layers and second dielectric layers, and a residual stop layer coplanar with the first semiconductor layer and in contact with the second semiconductor layer.

### Claim 10 (depends on 9)

The 3D memory device of claim 9, wherein the word line direction is perpendicular to the bit line direction in the plan view.

### Claim 11 (depends on 9)

The 3D memory device of claim 9, wherein the stabilization structure further comprises a residual sacrificial layer coplanar with the first semiconductor layer.

### Claim 12 (depends on 9)

The 3D memory device of claim 9, further comprising a source contact in contact with the second semiconductor layer without in contact with the first semiconductor layer.

### Claim 13

A method for forming a three-dimensional (3D) memory device, comprising:
forming a stop layer on a substrate;
forming a sacrificial layer on the stop layer;
forming a dielectric stack comprising vertically interleaved first dielectric layers and second dielectric layers on the sacrificial layer;
forming a plurality of channel structures each extending vertically through the dielectric stack and the sacrificial layer;
forming at least one opening extending laterally in a word line direction and vertically through the dielectric stack to expose the sacrificial layer;
replacing, through the at least one opening, part of the sacrificial layer and the stop layer with a semiconductor layer; and
replacing, through the at least one opening, part of the dielectric stack with a memory stack by replacing parts of the second dielectric layers with conductive layers to form a stabilization structure comprising:
a remainder of the stop layer in contact with the substrate,
a remainder of the sacrificial layer on the remainder of the stop layer, and
a remainder of the dielectric stack that extends laterally in the word line direction.

### Claim 14 (depends on 13)

The method of claim 13, wherein replacing the part of the dielectric stack with the memory stack comprises:
etching, through the at least one opening, the parts of the second dielectric layers to form recesses, leaving remainders of the second dielectric layers intact; and
depositing, through the at least one opening, the conductive layers into the recesses.

### Claim 15 (depends on 13)

The method of claim 13, wherein the stabilization structure is formed laterally between two openings of the at least one opening.

### Claim 16 (depends on 13)

The method of claim 13, wherein replacing the parts of the sacrificial layer and the stop layer with the semiconductor layer comprises:
sequentially etching, through the at least one opening, the part of the sacrificial layer and the part of the stop layer to form a cavity, leaving the remainders of the sacrificial layer and the stop layer intact; and
depositing, through the at least one opening, the semiconductor layer into the cavity.

### Claim 17 (depends on 13)

The method of claim 13, wherein the sacrificial layer comprises polysilicon or silicon nitride, the stop layer comprises silicon oxide, and the semiconductor layer comprises polysilicon.

### Claim 18 (depends on 13)

The method of claim 13, wherein
the at least one opening comprises at least one slit extending laterally; and
the method further comprises, after replacing the part of the dielectric stack with the memory stack, forming at least one slit structure in the at least one opening.

### Claim 19 (depends on 13)

The method of claim 13, further comprising forming a source contact in contact with the substrate without in contact with the semiconductor layer.

### Claim 20 (depends on 13)

The method of claim 13, further comprising filling the at least one opening with a dielectric material.