# US 12,010,833 B2 · Method and structure for reduce OTP cell area and leakage

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- Number: US 12,010,833 B2
- Document ID: US12010833B2
- Status: Granted
- Kind: B2
- Application number: 18/353,351
- Filed: 2023-07-17
- Published: 2023-11-09
- Granted: 2024-06-11
- Earliest claimed: 2020-02-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Meng-Sheng Chang; Chia-En Huang; Shao-Yu Chou; Yih Wang
- Web page: https://patentgrep.com/patent/US12010833B2

## CPC

- H10B 20/20: Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10D 89/10: Integrated device layouts
- H10W 20/43: Layouts of interconnections
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- H10B: ELECTRONIC MEMORY DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

## Claims

### Claim 1

A memory device comprising:
a first memory cell in a first cell row, the first memory cell comprising:
a first active region extending in a first direction,
a first continuous polysilicon line over active region edge (“CPODE”);
a first polysilicon line associated with a first read word line;
a second polysilicon line associated with a second read word line; and
a third polysilicon line associated with a first program word line; and
a second memory cell in a second cell row, the second memory cell comprising:
a second active region extending in the first direction;
a second CPODE;
a fourth polysilicon line associated with a second program word line;
a fifth polysilicon line associated with a third read word line; and
a sixth polysilicon line associated with a fourth read word line,
wherein the first cell is shifted by one polysilicon line pitch in the first direction with respect to the second cell.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first cell further comprises a third CPODE adjacent to the first CPODE.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the second cell further comprises a third CPODE adjacent to the second CPODE.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the first CPODE is formed at a CPODE degree with respect to the first polysilicon line, wherein the CPODE degree is greater than or equal to 45° and less than or equal to 135°.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the second CPODE is formed at a CPODE degree with respect to the fourth polysilicon line, wherein the CPODE degree is greater than or equal to 45° and less than or equal to 135°.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the first polysilicon line is connected to the fifth polysilicon line in a second direction perpendicular to the first direction, and the second polysilicon line is connected to the sixth polysilicon line in the second direction.

### Claim 7 (depends on 1)

The memory device of claim 1, further comprising a first metal over diffusion layer between the first CPODE and the first polysilicon line, a second metal over diffusion layer between the first polysilicon line and the second polysilicon line, and a third metal over diffusion layer between the second polysilicon line and the third polysilicon line.

### Claim 8

A memory device comprising:
a first memory cell in a first cell row, the first memory cell comprising:
a first active region extending in a first direction,
a first continuous polysilicon line over active region edge (“CPODE”);
a first polysilicon line associated with a first read word line;
a second polysilicon line associated with a second read word line; and
a third polysilicon line associated with a first program word line; and
a second memory cell in a second cell row, the second memory cell comprising:
a second active region extending in the first direction;
a second CPODE;
a fourth polysilicon line associated with a second program word line;
a fifth polysilicon line associated with a third read word line; and
a sixth polysilicon line associated with a fourth read word line,
wherein the first cell is shifted in the first direction relative to the second cell.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the first cell further comprises a third CPODE adjacent to the first CPODE.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the second cell further comprises a third CPODE adjacent to the second CPODE.

### Claim 11 (depends on 8)

The memory device of claim 8, wherein the first CPODE is formed at a CPODE degree with respect to the first polysilicon line, wherein the CPODE degree is greater than or equal to 45° and less than or equal to 135°.

### Claim 12 (depends on 8)

The memory device of claim 8, wherein the second CPODE is formed at a CPODE degree with respect to the fourth polysilicon line, wherein the CPODE degree is greater than or equal to 45° and less than or equal to 135°.

### Claim 13 (depends on 8)

The memory device of claim 8, wherein the first polysilicon line is connected to the fifth polysilicon line in a second direction perpendicular to the first direction, and the second polysilicon line is connected to the sixth polysilicon line in the second direction.

### Claim 14

A memory device comprising:
a first memory cell in a first cell row, the first memory cell comprising:
a first active region extending in a first direction,
a first continuous polysilicon line over active region edge (“CPODE”);
a first polysilicon line associated with a first read word line;
a second polysilicon line associated with a second read word line; and
a third polysilicon line associated with a first program word line; and
a second memory cell in a second cell row, the second memory cell comprising:
a second active region extending in the first direction;
a second CPODE;
a fourth polysilicon line associated with a second program word line;
a fifth polysilicon line associated with a third read word line; and
a sixth polysilicon line associated with a fourth read word line,
wherein either the first cell or the second cell is shifted by at least one polysilicon line pitch with respect to the second cell or the first cell, respectively.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the first cell further comprises a third CPODE adjacent to the first CPODE.

### Claim 16 (depends on 14)

The memory device of claim 14, wherein the second cell further comprises a third CPODE adjacent to the second CPODE.

### Claim 17 (depends on 14)

The memory device of claim 14, wherein the first CPODE is formed at a CPODE degree with respect to the first polysilicon line, wherein the CPODE degree is greater than or equal to 45° and less than or equal to 135°.

### Claim 18 (depends on 14)

The memory device of claim 14, wherein the second CPODE is formed at a CPODE degree with respect to the fourth polysilicon line, wherein the CPODE degree is greater than or equal to 45° and less than or equal to 135°.

### Claim 19 (depends on 14)

The memory device of claim 14, wherein upon placing the first cell and the second cell on a layout, the first polysilicon line is connected to the fifth polysilicon line in a second direction perpendicular to a first direction in which the first cell or the second cell is shifted, and the second polysilicon line is connected to the sixth polysilicon line in the second direction.

### Claim 20 (depends on 14)

The memory device of claim 14, further comprising:
a first metal over diffusion layer between the first CPODE and the first polysilicon line;
a second metal over diffusion layer between the first polysilicon line and the second polysilicon line; and
a third metal over diffusion layer between the second polysilicon line and the third polysilicon line.