# US 12,010,831 B2 · 3D DRAM with multiple memory tiers and vertically extending digit lines

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- Number: US 12,010,831 B2
- Document ID: US12010831B2
- Status: Granted
- Kind: B2
- Application number: 17/141,426
- Filed: 2021-01-05
- Published: 2022-07-07
- Granted: 2024-06-11
- Earliest claimed: 2021-01-05
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yuan He; Jiyun Li
- Web page: https://patentgrep.com/patent/US12010831B2

## CPC

- H10B 12/50: {Peripheral circuit region structures}
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- H10B 12/05: {Making the transistor}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/482: {Bit lines}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Some embodiments include an integrated assembly having a memory array over a base. The memory array includes a three-dimensional arrangement of memory cells. Sense amplifiers are associated with the base and are directly under the memory array. Vertically-extending digit lines pass through the arrangement of the memory cells and are coupled with the sense amplifiers. Some embodiments include an integrated assembly having a memory bank containing 64 memory chunks arranged in a 16×4 configuration. Some embodiments include an integrated assembly having a memory bank which contains 512 megabytes divided amongst 64 memory chunks which each have 8 megabytes. The 64 memory chunks are arranged in a configuration having multiple rows which each contain a two or more of the memory chunks.

## Claims

### Claim 1

An integrated assembly, comprising:
a memory array over a base; the memory array comprising a three-dimensional arrangement of memory cells;
sense amplifiers associated with the base and being directly under the memory array;
vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section; and
wherein the memory cells include horizontally-extending access devices coupled with storage elements.

### Claim 2 (depends on 1)

The integrated assembly of claim 1 wherein the memory array includes 128 vertically-stacked tiers of the memory cells and wherein the memory array comprises 128 wordlines associated with each of the individual tiers of the memory cells.

### Claim 3 (depends on 1)

The integrated assembly of claim 1 wherein the digit lines are subdivided amongst comparative sets, with each of the comparative sets comprising a first comparative digit line and a second comparative digit line comparatively coupled to the first comparative digit line through one of the sense amplifiers.

### Claim 4 (depends on 3)

The integrated assembly of claim 3 wherein multiple of the comparative sets of the digit lines are coupled with a single one of the sense amplifiers.

### Claim 5 (depends on 1)

The integrated assembly of claim 1 wherein the access devices are the transistors.

### Claim 6 (depends on 1)

The integrated assembly of claim 1 wherein the storage elements are capacitors.

### Claim 7 (depends on 1)

The integrated assembly of claim 1 wherein the storage elements comprise at least one of the following:
resistive-memory devices, conductive-bridging devices, phase-change-memory devices, and programmable metallization cells.

### Claim 8 (depends on 1)

The integrated assembly of claim 1 wherein the vertically-extending digit lines extend directly through source/drain regions of transistors in the memory cells.

### Claim 9 (depends on 1)

The integrated assembly of claim 1 further comprising a conductive plate extending vertically along the three-dimensional arrangement of memory cells.

### Claim 10 (depends on 9)

The integrated assembly of claim 9 wherein the conductive plate is configured to drain excess carriers from the channel regions of transistors.

### Claim 11 (depends on 1)

The integrated assembly of claim 1 wherein an entirety of the structure for the vertically-extending digit lines extend only vertically.

### Claim 12 (depends on 1)

The integrated assembly of claim 1 further comprising a conductive plate that is a separate structure from the structure of the storage elements.

### Claim 13 (depends on 1)

The integrated assembly of claim 1 further comprising a conductive plate spaced from the source/drain regions.

### Claim 14 (depends on 1)

The integrated assembly of claim 1 wherein the storage elements are spaced from the source/drain regions.

### Claim 15

An integrated assembly, comprising:
a memory array over a base; the memory array comprising a three-dimensional arrangement of memory cells;
sense amplifiers associated with the base and being directly under the memory array;
vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
a channel region between the source/drain regions and comprising at least two sides, a gate region operatedly adjacent only one side of the channel region;
wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section; and
wherein the memory array includes 128 vertically-stacked tiers of the memory cells and wherein the memory array comprises 128 wordlines associated with each of the individual tiers of the memory cells.

### Claim 16

An integrated assembly, comprising:
a memory array over a base; the memory array comprising a three-dimensional arrangement of memory cells;
sense amplifiers associated with the base and being directly under the memory array;
vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section; and
wherein the vertically-extending digit lines extend directly through source/drain regions of transistors in the memory cells.

### Claim 17 (depends on 16)

The integrated assembly of claim 16 further comprising:
a conductive plate coupled to the memory cells; and
storage elements coupled to the memory cells, the storage elements being separate structures from the conductive plate.

### Claim 18 (depends on 16)

The integrated assembly of claim 16 further comprising a conductive plate spaced from the source/drain regions having the vertically-extending digit lines.

### Claim 19 (depends on 16)

The integrated assembly of claim 16 wherein the storage elements are spaced from the source/drain regions.

### Claim 20

An integrated assembly, comprising:
a memory array over a base; the memory array comprising a three-dimensional arrangement of memory cells;
sense amplifiers associated with the base and being directly under the memory array;
vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
a conductive plate extending vertically along the three-dimensional arrangement of memory cells; and
storage elements coupled with the memory cells, the storage elements being separate structures from the conductive plate.

### Claim 21 (depends on 20)

The integrated assembly of claim 20 wherein the conductive plate is configured to drain excess carriers from the channel regions of transistors.

### Claim 22 (depends on 20)

The integrated assembly of claim 20 wherein the conductive plate is spaced from the source/drain regions.

### Claim 23 (depends on 20)

The integrated assembly of claim 20 further comprising storage elements that are spaced from the source/drain regions.

### Claim 24

An integrated assembly, comprising:
a memory array over a base; the memory array comprising a three-dimensional arrangement of memory cells;
sense amplifiers associated with the base and being directly under the memory array;
vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section; and
wherein an entirety of the structure for the vertically-extending digit lines extend only vertically.

### Claim 25 (depends on 24)

The integrated assembly of claim 24 further comprising;
a conductive plate; and
storage elements that are separate structures from the conductive plate.

### Claim 26 (depends on 24)

The integrated assembly of claim 24 further comprising a conductive plate spaced from the source/drain regions.

### Claim 27 (depends on 24)

The integrated assembly of claim 24 further comprising storage elements that are spaced from the source/drain regions.

### Claim 28

An integrated assembly, comprising:
a memory array over a base; the memory array comprising a three-dimensional arrangement of memory cells;
sense amplifiers associated with the base and being directly under the memory array;
vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section; and
wherein the digit lines are subdivided amongst comparative sets, with each of the comparative sets comprising a first comparative digit line and a second comparative digit line comparatively coupled to the first comparative digit line through one of the sense amplifiers.

### Claim 29 (depends on 28)

The integrated assembly of claim 28 wherein multiple of the comparative sets of the digit lines are coupled with a single one of the sense amplifiers.

### Claim 30 (depends on 28)

The integrated assembly of claim 28 further comprising;
a conductive plate; and
storage elements that are separate structures from the conductive plate.

### Claim 31 (depends on 28)

The integrated assembly of claim 28 further comprising a conductive plate spaced from the source/drain regions.

### Claim 32 (depends on 28)

The integrated assembly of claim 28 further comprising storage elements that are spaced from the source/drain regions.

### Claim 33

An integrated assembly, comprising:
a memory array over a base; the memory array comprising a three-dimensional arrangement of memory cells;
sense amplifiers associated with the base and being directly under the memory array;
vertically-extending digit lines passing through source/drain regions of the memory cells and being coupled with the sense amplifiers;
a channel region between the source/drain regions and comprising at least two sides, a gate region operatedly adjacent only one side of the channel region;
wherein each source/drain region comprises an area in a horizontal cross section substantially larger than an area of each digit line in the horizontal cross section;
wherein the memory cells include horizontally-extending access devices coupled with storage elements; and
wherein the memory array includes 128 vertically-stacked tiers of the memory cells and wherein the memory array comprises 128 wordlines associated with each of the individual tiers of the memory cells.