# US 12,010,828 B2 · Semiconductor memory device and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,010,828 B2 - Document ID: US12010828B2 - Status: Granted - Kind: B2 - Application number: 17/382,844 - Filed: 2021-07-22 - Published: 2022-05-19 - Granted: 2024-06-11 - Earliest claimed: 2020-11-16 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seungjae Jung; Kwang-Ho Park - Web page: https://patentgrep.com/patent/US12010828B2 ## CPC - H10B 12/05: {Making the transistor} - H10B 12/03: {Making the capacitor or connections thereto} - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H10B 12/488: {Word lines} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory device includes a substrate and a stack including word lines and interlayer insulating patterns alternatingly stacked on the substrate. The word lines extend in a first direction. Semiconductor patterns cross the word lines and have longitudinal axes parallel to a second direction. The semiconductor patterns are spaced apart from each other in the first direction and a third direction. Bit lines extend in the third direction and are spaced apart from each other in the first direction. Each of the bit lines contacts first side surfaces of the semiconductor patterns spaced apart from each other in the third direction. Data storage elements, which are respectively provided between vertically adjacent interlayer insulating patterns and contact second side surfaces opposite to the first side surfaces, and substrate impurity layers provided in portions of the substrate at both sides of the stack, are included. ## Claims ### Claim 1 A semiconductor memory device, comprising: a substrate; a stack including a plurality of word lines and a plurality of interlayer insulating patterns, which are alternatingly stacked on the substrate, wherein the word lines extend in a first direction substantially parallel to a top surface of the substrate; a plurality of semiconductor patterns crossing the word lines and having longitudinal axes that are substantially parallel to a second direction, wherein the semiconductor patterns are spaced apart from each other in the first direction and a third direction that is substantially perpendicular to the top surface of the substrate; a plurality of bit lines extending in the third direction and spaced apart from each other in the first direction, wherein each of the bit lines is in contact with first side surfaces of the semiconductor patterns that are spaced apart from each other in the third direction; a plurality of data storage elements, wherein the data storage elements are respectively provided between vertically adjacent patterns of the interlayer insulating patterns and are in contact with second side surfaces opposite to the first side surfaces of the semiconductor patterns; and a plurality of substrate impurity layers provided in portions of the substrate at both sides of the stack. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the substrate impurity layers include at least one of boron (B), carbon (C), or fluorine (F). ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein an impurity concentration in the substrate impurity layers decreases as a distance from a surface of the substrate increases. ### Claim 4 (depends on 1) The semiconductor memory device of claim 1, wherein the substrate impurity layers extend in the first direction and are substantially parallel to each other. ### Claim 5 (depends on 1) The semiconductor memory device of claim 1, wherein the semiconductor patterns are formed of single crystalline silicon. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, wherein each of the semiconductor patterns comprises first and second source/drain regions, which are spaced apart from each other in the second direction, and a channel region disposed between the first and second source/drain regions, and a width of each of the semiconductor patterns in the first direction is larger at the channel region than at the first and second source/drain regions. ### Claim 7 (depends on 1) The semiconductor memory device of claim 1, wherein each of the word lines extends in the first direction and surrounds portions of the semiconductor patterns which are located at a same level thereof. ### Claim 8 (depends on 1) The semiconductor memory device of claim 1, wherein the data storage elements comprise: a plurality of storage electrodes, which are respectively in contact with the second side surfaces of the semiconductor patterns and extend substantially parallel to the top surface of the substrate; a dielectric layer conformally covering the storage electrodes; and a plate electrode disposed on the dielectric layer. ### Claim 9 (depends on 1) The semiconductor memory device of claim 1, further comprising: a plurality of first insulating separation patterns, which are spaced apart from each other in the first direction and are provided between the bit lines; and a plurality of second insulating separation patterns, which are spaced apart from each other in the first direction and are provided between the data storage elements, wherein the first and second insulating separation patterns extend in the third direction and penetrate the stack. ### Claim 10 (depends on 9) The semiconductor memory device of claim 9, wherein a width of each of the semiconductor patterns in the first direction is smaller than a distance between the first insulating separation patterns which are adjacent to each other in the first direction. ### Claim 11 (depends on 9) The semiconductor memory device of claim 9, wherein a width of each of the word lines in the second direction is smaller at a region between the first and second insulating separation patterns than at a region on each of the semiconductor patterns. ### Claim 12 A semiconductor memory device, comprising: a substrate; a stack including a plurality of word lines and a plurality of interlayer insulating patterns, which are alternatingly stacked on the substrate, wherein the word lines extend in a first direction substantially parallel to a top surface of the substrate; a plurality of semiconductor patterns crossing the word lines and having longitudinal axes that are substantially parallel to a second direction, wherein the semiconductor patterns are spaced apart from each other in the first direction and a third direction that is substantially perpendicular to the top surface of the substrate; a plurality of bit lines extending in the third direction and spaced apart from each other in the first direction, wherein each of the bit lines is in contact with first side surfaces of the semiconductor patterns that are spaced apart from each other in the third direction; a plurality of data storage elements, wherein the data storage elements are respectively provided between vertically adjacent patterns of the interlayer insulating patterns and are in contact with second side surfaces opposite to the first side surfaces of the semiconductor patterns, wherein each of the semiconductor patterns comprises first source/drain regions and second source/drain regions, which are spaced apart from each other in the second direction, and a channel region disposed between the first and second source/drain regions, the channel regions of the semiconductor patterns have a first thickness in the third direction, and the first source/drain regions of the semiconductor patterns have a second thickness that is substantially equal to or greater than the first thickness in the third direction; and a plurality of substrate impurity layers provided in portions of the substrate at both sides of the stack. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, wherein the substrate impurity layers comprise at least one of boron (B), carbon (C), or fluorine (F). ### Claim 14 (depends on 12) The semiconductor memory device of claim 12, wherein the semiconductor patterns comprise a same semiconductor material as the substrate. ### Claim 15 (depends on 12) The semiconductor memory device of claim 12, wherein the first and second side surfaces of the semiconductor patterns have a substantially flat shape. ### Claim 16 (depends on 12) The semiconductor memory device of claim 12, further comprising: a plurality of first insulating separation patterns, which are spaced apart from each other in the first direction and are provided between the bit lines; and a plurality of second insulating separation patterns, which are spaced apart from each other in the first direction and are provided between the data storage elements, wherein the first and second insulating separation patterns extend in the third direction to penetrate the stack. ### Claim 17 (depends on 12) The semiconductor memory device of claim 12, wherein each of the semiconductor patterns comprises first source/drain regions and second source/drain regions, which are spaced apart from each other in the second direction, and a channel region disposed therebetween, and a width of each of the semiconductor patterns in the first direction is larger at the channel region than at the first and second source/drain regions. ### Claim 18 A semiconductor memory device, comprising: a substrate; a first stack disposed on the substrate; a second stack disposed on the substrate, wherein each of the first and second stacks comprises a plurality of word lines, which extend in a first direction and are stacked on the substrate with interlayer insulating patterns interposed therebetween; a plurality of semiconductor patterns having longitudinal axes, which are substantially parallel to a second direction crossing the word lines, wherein the semiconductor patterns are disposed on the substrate and are spaced apart from each other in the first direction, the second direction, and a third direction, which is substantially perpendicular to a top surface of the substrate; a plurality of bit lines extending in the third direction and spaced apart from each other in the first direction, wherein the bit lines comprise first bit lines crossing the word lines of the first stack and second bit lines crossing the word lines of the second stack; a plurality of first storage electrodes respectively provided between vertically adjacent patterns of the interlayer insulating patterns of the first stack; a plurality of second storage electrodes respectively provided between vertically adjacent patterns of the interlayer insulating patterns of the second stack; a plate electrode, which is provided between the first and second stacks and covers the first and second storage electrodes in common; a dielectric layer disposed between the first and second storage electrodes and the plate electrode; a plurality of first insulating separation patterns, which are spaced apart from each other in the first direction and are provided between the first bit lines and between the second bit lines; a plurality of second insulating separation patterns, which are spaced apart from each other in the first direction and are provided between the first storage electrodes and between the second storage electrodes; and a plurality of substrate impurity layers provided in portions of the substrate at both sides of the first and second stacks, wherein the substrate impurity layers include at least one of boron (B), carbon (C), or fluorine (F). ### Claim 19 (depends on 18) The semiconductor memory device of claim 18, wherein each of the semiconductor patterns comprises first source/drain regions and second source/drain regions, which are spaced apart from each other in the second direction, and a channel region disposed therebetween, the channel regions of the semiconductor patterns have a first thickness in the third direction, and the first source/drain regions of the semiconductor patterns have a second thickness that is substantially equal to or larger than the first thickness.