# US 12,010,826 B2 · Semiconductor device having a butted contact and method of forming

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- Number: US 12,010,826 B2
- Document ID: US12010826B2
- Status: Granted
- Kind: B2
- Application number: 18/184,036
- Filed: 2023-03-15
- Published: 2023-07-13
- Granted: 2024-06-11
- Earliest claimed: 2018-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: You Che Chuang; Chih-Ming Lee; Hsin-Chi Chen; Hsun-Ying Huang
- Web page: https://patentgrep.com/patent/US12010826B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10D 89/10: Integrated device layouts
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The first butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate structure.

## Claims

### Claim 1

A semiconductor structure, comprising;
a first transistor comprising a first gate structure over a first active region in a substrate, wherein the first gate structure comprises a first gate stack and gate spacers;
a second active region in the substrate, wherein the second active region is isolated from the first active region; and
a first butted contact, wherein the first butted contact comprises:
a first portion extending in a first direction and overlapping the second active region, and
a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate stack.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the second portion extends in a second direction different from the first direction.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising a second transistor comprising a second gate structure over the second active region in the substrate.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, further comprising a source/drain (S/D) feature between the first gate structure and the second gate structure.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the first butted contact is in direct contact with the S/D feature.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, further comprising an isolation structure in the substrate.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the first gate structure partially overlaps the isolation structure.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the first transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the first transistor comprises an n-type metal oxide semiconductor (NMOS) transistor.

### Claim 10

A static random access memory (SRAM) cell, comprising:
a first pull-up (PU) transistor comprising a first gate structure;
a first pull-down (PD) transistor comprising the first gate structure;
a second PU transistor comprising a second gate structure, wherein the second gate structure comprises a gate stack and gate spacers;
a second PD transistor comprising the second gate structure; and
a first butted contact, wherein the first butted contact electrically connects a first terminal of the first PU transistor to the second gate structure, wherein the first butted contact directly contacts each of a top surface and a sidewall of the gate stack.

### Claim 11 (depends on 10)

The SRAM cell of claim 10, further comprising a second butted contact wherein the second butted contact electrically connects a second terminal of the second PU transistor to the first gate structure.

### Claim 12 (depends on 11)

The SRAM cell of claim 11, wherein the second butted contact directly contacts each of a top surface and a sidewall of the first gate structure.

### Claim 13 (depends on 11)

The SRAM cell of claim 11, wherein the first butted contact comprises:
a first portion extending in a first direction parallel to the second gate structure; and
a second portion extending in a second direction perpendicular to the second gate structure.

### Claim 14 (depends on 11)

The SRAM cell of claim 11, further comprising a first contact structure electrically connected to a third terminal of the second PU transistor, wherein the third terminal is on an opposite side of the second gate structure from the second terminal.

### Claim 15 (depends on 10)

The SRAM cell of claim 10, wherein the first butted contact comprises:
a first portion extending in a first direction parallel to the second gate structure; and
a second portion extending in a second direction perpendicular to the second gate structure.

### Claim 16 (depends on 10)

The SRAM cell of claim 10, further comprising a first contact structure electrically connected to a second terminal of the first PU transistor, wherein the second terminal is on an opposite side of the first gate structure from the first terminal.

### Claim 17 (depends on 10)

The SRAM cell of claim 10, wherein the first butted contact comprises:
a contact liner; and
a contact plug, wherein the contact liner surrounds the contact plug.

### Claim 18

A method of making a semiconductor structure, the method comprising;
forming a first gate structure over a first active region in a substrate, wherein the first gate structure comprises a first gate stack and gate spacers;
forming a second active region in the substrate, wherein the second active region is isolated from the first active region;
depositing a dielectric layer over the substrate, wherein the dielectric layer extends over the first active region and the second active region;
etching the dielectric layer to form an opening, wherein the opening exposes the second active region, a top surface of the first gate structure, and a sidewall of the first gate structure; and
depositing a conductive material in the opening, wherein the conductive material directly contacts the top surface of the first gate structure and the sidewall of the first gate stack.

### Claim 19 (depends on 18)

The method of claim 18, wherein etching the dielectric layer comprises forming the first opening having:
a first portion extending parallel to the first gate structure, and
a second portion extending perpendicular to the first gate structure.

### Claim 20 (depends on 18)

The method of claim 18, further comprising forming a second gate structure over the second active region, wherein etching the dielectric layer comprises forming the opening exposing a top surface of the substrate between the first gate structure and the second gate structure.